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-rw-r--r--src/northbridge/intel/haswell/romstage.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c
index 5b025eba24..3227c02287 100644
--- a/src/northbridge/intel/haswell/romstage.c
+++ b/src/northbridge/intel/haswell/romstage.c
@@ -4,11 +4,14 @@
#include <console/console.h>
#include <cf9_reset.h>
#include <device/device.h>
+#include <device/mmio.h>
#include <timestamp.h>
#include <cpu/x86/lapic.h>
#include <cbmem.h>
#include <commonlib/helpers.h>
#include <romstage_handoff.h>
+#include <security/intel/txt/txt.h>
+#include <security/intel/txt/txt_register.h>
#include <cpu/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/chip.h>
#include <northbridge/intel/haswell/haswell.h>
@@ -108,12 +111,27 @@ void mainboard_romstage_entry(void)
report_platform_info();
+ if (CONFIG(INTEL_TXT))
+ intel_txt_romstage_init();
+
copy_spd(&pei_data);
sdram_initialize(&pei_data);
timestamp_add_now(TS_AFTER_INITRAM);
+ if (CONFIG(INTEL_TXT)) {
+ printk(BIOS_DEBUG, "Check TXT_ERROR register after MRC\n");
+
+ intel_txt_log_acm_error(read32((void *)TXT_ERROR));
+
+ intel_txt_log_spad();
+
+ intel_txt_memory_has_secrets();
+
+ txt_dump_regions();
+ }
+
post_code(0x3b);
intel_early_me_status();