diff options
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/amdfam10/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/amdfam10/ht_config.c (renamed from src/northbridge/amd/amdfam10/conf.c) | 38 | ||||
| -rw-r--r-- | src/northbridge/amd/amdfam10/ht_config.h | 62 | ||||
| -rw-r--r-- | src/northbridge/amd/amdfam10/northbridge.c | 8 |
4 files changed, 88 insertions, 22 deletions
diff --git a/src/northbridge/amd/amdfam10/Makefile.inc b/src/northbridge/amd/amdfam10/Makefile.inc index fdbfa1222a..65bdc0363c 100644 --- a/src/northbridge/amd/amdfam10/Makefile.inc +++ b/src/northbridge/amd/amdfam10/Makefile.inc @@ -3,6 +3,8 @@ ramstage-y += misc_control.c romstage-y += amdfam10_util.c ramstage-y += amdfam10_util.c +ramstage-y += ht_config.c + ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += get_pci1234.c diff --git a/src/northbridge/amd/amdfam10/conf.c b/src/northbridge/amd/amdfam10/ht_config.c index ba488bf861..cfd8a24526 100644 --- a/src/northbridge/amd/amdfam10/conf.c +++ b/src/northbridge/amd/amdfam10/ht_config.c @@ -17,14 +17,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -typedef struct amdfam10_sysconf_t sys_info_conf_t; +#include <arch/io.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci_ops.h> -struct dram_base_mask_t { - u32 base; //[47:27] at [28:8] - u32 mask; //[47:27] at [28:8] and enable at bit 0 -}; +#include <cpu/amd/amdfam10_sysconf.h> +#include "northbridge.h" +#include "amdfam10.h" +#include "ht_config.h" -static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) +struct dram_base_mask_t get_dram_base_mask(u32 nodeid) { struct dram_base_mask_t d; device_t dev = __f1_dev[0]; @@ -45,7 +48,7 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) } -static void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, +void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 busn_min, u32 busn_max, u32 segbit, u32 nodes) { @@ -62,7 +65,7 @@ static void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, } } -static void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, +void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 busn_min, u32 busn_max, u32 nodes) { u32 i; @@ -74,7 +77,7 @@ static void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, } #if CONFIG_PCI_BUS_SEGN_BITS -static u32 check_segn(device_t dev, u32 segbusn, u32 nodes, +u32 check_segn(device_t dev, u32 segbusn, u32 nodes, sys_info_conf_t *sysinfo) { //check segbusn here, We need every node have the same segn @@ -95,7 +98,7 @@ static u32 check_segn(device_t dev, u32 segbusn, u32 nodes, } #endif -static u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo) +u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo) { u32 tempreg; u32 ht_c_index = 0; @@ -126,7 +129,7 @@ static u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo) return -1; } -static void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index, +void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index, u32 busn_min, u32 busn_max, sys_info_conf_t *sysinfo) { @@ -136,7 +139,7 @@ static void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index, } -static u32 get_io_addr_index(u32 nodeid, u32 linkn) +u32 get_io_addr_index(u32 nodeid, u32 linkn) { u32 index; @@ -151,7 +154,7 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn) return 0; } -static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) +u32 get_mmio_addr_index(u32 nodeid, u32 linkn) { u32 index; @@ -166,7 +169,8 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) return 0; } -static void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, + +void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 io_min, u32 io_max) { u32 val; @@ -184,7 +188,7 @@ static void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, } -static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, +void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max) { u32 val; @@ -202,7 +206,7 @@ static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -229,7 +233,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, pci_write_config32(__f1_dev[i], reg, tempreg); } -static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) +void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) { u32 i; u32 tempreg; diff --git a/src/northbridge/amd/amdfam10/ht_config.h b/src/northbridge/amd/amdfam10/ht_config.h new file mode 100644 index 0000000000..9b82f545b6 --- /dev/null +++ b/src/northbridge/amd/amdfam10/ht_config.h @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +typedef struct amdfam10_sysconf_t sys_info_conf_t; + +/* FIXME */ +extern device_t __f1_dev[]; + +struct dram_base_mask_t { + u32 base; //[47:27] at [28:8] + u32 mask; //[47:27] at [28:8] and enable at bit 0 +}; + +struct dram_base_mask_t get_dram_base_mask(u32 nodeid); + +void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, + u32 busn_min, u32 busn_max, u32 segbit, + u32 nodes); +void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, + u32 busn_min, u32 busn_max, u32 nodes); +u32 check_segn(device_t dev, u32 segbusn, u32 nodes, + sys_info_conf_t *sysinfo); + +void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index, + u32 busn_min, u32 busn_max, + sys_info_conf_t *sysinfo); + +u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo); + + +void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, + u32 io_min, u32 io_max); + +void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, + u32 mmio_min, u32 mmio_max); + + +u32 get_io_addr_index(u32 nodeid, u32 linkn); +u32 get_mmio_addr_index(u32 nodeid, u32 linkn); + +void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, + u32 io_min, u32 io_max); + +void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes); + + diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index cbeddf2aad..503dcf9d65 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -32,6 +32,7 @@ #include <cpu/x86/lapic.h> #include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam10_sysconf.h> #if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> @@ -39,14 +40,13 @@ #endif #include "northbridge.h" - #include "amdfam10.h" +#include "ht_config.h" #if CONFIG_HW_MEM_HOLE_SIZEK != 0 #include <cpu/amd/model_10xxx_rev.h> #endif -#include <cpu/amd/amdfam10_sysconf.h> #if CONFIG_AMD_SB_CIMX #include <sb_cimx.h> #endif @@ -55,7 +55,7 @@ struct amdfam10_sysconf_t sysconf; #define FX_DEVS NODE_NUMS static device_t __f0_dev[FX_DEVS]; -static device_t __f1_dev[FX_DEVS]; +device_t __f1_dev[FX_DEVS]; static device_t __f2_dev[FX_DEVS]; static device_t __f4_dev[FX_DEVS]; static unsigned fx_devs=0; @@ -127,8 +127,6 @@ static u32 amdfam10_nodeid(device_t dev) #endif } -#include "conf.c" - static void set_vga_enable_reg(u32 nodeid, u32 linkn) { u32 val; |