diff options
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/amdfam10/amdfam10.h | 5 | ||||
| -rw-r--r-- | src/northbridge/amd/amdfam10/resourcemap.c | 88 |
2 files changed, 49 insertions, 44 deletions
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 163d9dfdcc..e1c88c9140 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -26,6 +26,11 @@ struct DCTStatStruc; struct MCTStatStruc; + +/* Definitions for setup_resourcemap() variants. */ + +#define ADDRMAP_REG(r) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, r) + #define RES_PCI_IO 0x10 #define RES_PORT_IO_8 0x22 #define RES_PORT_IO_32 0x20 diff --git a/src/northbridge/amd/amdfam10/resourcemap.c b/src/northbridge/amd/amdfam10/resourcemap.c index 362872b261..fa4ab3cfd7 100644 --- a/src/northbridge/amd/amdfam10/resourcemap.c +++ b/src/northbridge/amd/amdfam10/resourcemap.c @@ -45,14 +45,14 @@ static void setup_default_resource_map(void) * This field defines the upper address bits of a 40 bit * address that define the end of the DRAM region. */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, + ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, + ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, + ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, + ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, + ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, + ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, + ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -83,14 +83,14 @@ static void setup_default_resource_map(void) * This field defines the upper address bits of a 40-bit * address that define the start of the DRAM region. */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, + ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -125,14 +125,14 @@ static void setup_default_resource_map(void) * address that defines the end of a memory-mapped * I/O region n */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + ADDRMAP_REG(0x84), 0x00000048, 0x00000000, + ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, + ADDRMAP_REG(0x94), 0x00000048, 0x00000000, + ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, + ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, + ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, + ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -161,14 +161,14 @@ static void setup_default_resource_map(void) * address that defines the start of memory-mapped * I/O region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, + ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, + ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -195,10 +195,10 @@ static void setup_default_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, + ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, + ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -227,10 +227,10 @@ static void setup_default_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, + ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, + ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -270,10 +270,10 @@ static void setup_default_resource_map(void) * This field defines the highest bus number in * configuration regin i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0xff000003, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE0), 0x0000FC88, 0xff000003, + ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, + ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, }; u32 max; |