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-rw-r--r--src/northbridge/amd/amdk8/amdk8_f.h4
-rw-r--r--src/northbridge/amd/amdk8/coherent_ht.c24
-rw-r--r--src/northbridge/amd/amdk8/incoherent_ht.c42
-rw-r--r--src/northbridge/amd/amdk8/northbridge.c2
-rw-r--r--src/northbridge/amd/amdk8/raminit_f_dqs.c36
-rw-r--r--src/northbridge/amd/amdk8/raminit_test.c6
-rw-r--r--src/northbridge/amd/amdk8/setup_resource_map.c24
-rw-r--r--src/northbridge/amd/gx1/raminit.c32
-rw-r--r--src/northbridge/amd/gx2/pll_reset.c10
-rw-r--r--src/northbridge/amd/gx2/raminit.c16
-rw-r--r--src/northbridge/amd/lx/pll_reset.c2
-rw-r--r--src/northbridge/amd/lx/raminit.c14
-rw-r--r--src/northbridge/intel/e7501/debug.c42
-rw-r--r--src/northbridge/intel/e7501/raminit.c64
-rw-r--r--src/northbridge/intel/e7520/memory_initialized.c2
-rw-r--r--src/northbridge/intel/e7520/raminit.c42
-rw-r--r--src/northbridge/intel/e7525/raminit.c42
-rw-r--r--src/northbridge/intel/i3100/raminit.c32
-rw-r--r--src/northbridge/intel/i3100/raminit_ep80579.c122
-rw-r--r--src/northbridge/intel/i440bx/debug.c8
-rw-r--r--src/northbridge/intel/i440bx/raminit.c60
-rw-r--r--src/northbridge/intel/i440lx/raminit.c38
-rw-r--r--src/northbridge/intel/i82810/debug.c8
-rw-r--r--src/northbridge/intel/i82810/raminit.c34
-rw-r--r--src/northbridge/intel/i82830/raminit.c88
-rw-r--r--src/northbridge/intel/i855/debug.c28
-rw-r--r--src/northbridge/intel/i855/raminit.c28
-rw-r--r--src/northbridge/via/cn400/raminit.c52
-rw-r--r--src/northbridge/via/cn700/raminit.c16
-rw-r--r--src/northbridge/via/cx700/cx700_early_smbus.c20
-rw-r--r--src/northbridge/via/vt8601/raminit.c30
-rw-r--r--src/northbridge/via/vt8623/raminit.c52
-rw-r--r--src/northbridge/via/vx800/examples/romstage.c38
-rw-r--r--src/northbridge/via/vx800/vga.c2
-rw-r--r--src/northbridge/via/vx800/vx800_early_smbus.c30
35 files changed, 545 insertions, 545 deletions
diff --git a/src/northbridge/amd/amdk8/amdk8_f.h b/src/northbridge/amd/amdk8/amdk8_f.h
index ea4e8947f8..8b1b0a0af1 100644
--- a/src/northbridge/amd/amdk8/amdk8_f.h
+++ b/src/northbridge/amd/amdk8/amdk8_f.h
@@ -559,7 +559,7 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
for(i=0; i<sysinfo->nodes; i++) {
#ifdef __PRE_RAM__
- print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\r\n");
+ print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n");
#else
printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
#endif
@@ -576,7 +576,7 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
}
if(needs_reset) {
#ifdef __PRE_RAM__
- print_debug("mem trained failed\r\n");
+ print_debug("mem trained failed\n");
soft_reset();
#else
printk(BIOS_DEBUG, "mem trained failed\n");
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 66876c2148..39182854eb 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -111,7 +111,7 @@
static inline void print_linkn (const char *strval, uint8_t byteval)
{
- printk(BIOS_DEBUG, "%s%02x\r\n", strval, byteval);
+ printk(BIOS_DEBUG, "%s%02x\n", strval, byteval);
}
static void disable_probes(void)
@@ -149,7 +149,7 @@ static void disable_probes(void)
HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P;
pci_write_config32(NODE_HT(0), HT_TRANSACTION_CONTROL, val);
- print_spew("done.\r\n");
+ print_spew("done.\n");
}
@@ -200,7 +200,7 @@ static void enable_routing(u8 node)
val &= ~((1<<1)|(1<<0));
pci_write_config32(NODE_HT(node), 0x6c, val);
- print_spew(" done.\r\n");
+ print_spew(" done.\n");
}
static void fill_row(u8 node, u8 row, u32 value)
@@ -250,7 +250,7 @@ static void rename_temp_node(u8 node)
val |= node; /* new node */
pci_write_config32(NODE_HT(7), 0x60, val);
- print_spew(" done.\r\n");
+ print_spew(" done.\n");
}
static int verify_connection(u8 dest)
@@ -513,7 +513,7 @@ static void setup_remote_node(u8 node)
pci_write_config32(NODE_MP(7), reg, value);
}
- print_spew("done\r\n");
+ print_spew("done\n");
}
#endif /* CONFIG_MAX_PHYSICAL_CPUS > 1*/
@@ -652,7 +652,7 @@ static void setup_remote_row_indirect_group(const u8 *conn, int num)
static void setup_uniprocessor(void)
{
- print_spew("Enabling UP settings\r\n");
+ print_spew("Enabling UP settings\n");
#if CONFIG_LOGICAL_CPUS==1
unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3;
if (tmp>0) return;
@@ -1478,7 +1478,7 @@ static unsigned setup_smp(void)
{
unsigned nodes;
- print_spew("Enabling SMP settings\r\n");
+ print_spew("Enabling SMP settings\n");
nodes = setup_smp2();
#if CONFIG_MAX_PHYSICAL_CPUS > 2
@@ -1496,7 +1496,7 @@ static unsigned setup_smp(void)
nodes = setup_smp8();
#endif
- printk(BIOS_DEBUG, "%02x nodes initialized.\r\n", nodes);
+ printk(BIOS_DEBUG, "%02x nodes initialized.\n", nodes);
return nodes;
}
@@ -1515,14 +1515,14 @@ static unsigned verify_mp_capabilities(unsigned nodes)
#if CONFIG_MAX_PHYSICAL_CPUS > 2
case 0x02: /* MPCap */
if(nodes > 2) {
- print_err("Going back to DP\r\n");
+ print_err("Going back to DP\n");
return 2;
}
break;
#endif
case 0x00: /* Non SMP */
if(nodes >1 ) {
- print_err("Going back to UP\r\n");
+ print_err("Going back to UP\n");
return 1;
}
break;
@@ -1601,7 +1601,7 @@ static void coherent_ht_finalize(unsigned nodes)
* registers on Hammer A0 revision.
*/
- print_spew("coherent_ht_finalize\r\n");
+ print_spew("coherent_ht_finalize\n");
#if CONFIG_K8_REV_F_SUPPORT == 0
rev_a0 = is_cpu_rev_a0();
#endif
@@ -1642,7 +1642,7 @@ static void coherent_ht_finalize(unsigned nodes)
#endif
}
- print_spew("done\r\n");
+ print_spew("done\n");
}
static int apply_cpu_errata_fixes(unsigned nodes)
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index 2e68618100..6a85516211 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -26,7 +26,7 @@
static inline void print_linkn_in (const char *strval, uint8_t byteval)
{
- printk(BIOS_DEBUG, "%s%02x\r\n", strval, byteval);
+ printk(BIOS_DEBUG, "%s%02x\n", strval, byteval);
}
static uint8_t ht_lookup_capability(device_t dev, uint16_t val)
@@ -127,7 +127,7 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos)
uint32_t id;
freq_cap = pci_read_config16(dev, pos);
- printk(BIOS_SPEW, "pos=0x%x, unfiltered freq_cap=0x%x\r\n", pos, freq_cap);
+ printk(BIOS_SPEW, "pos=0x%x, unfiltered freq_cap=0x%x\n", pos, freq_cap);
freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
id = pci_read_config32(dev, 0);
@@ -157,8 +157,8 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos)
#endif
}
- printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\r\n", pos, freq_cap);
- //printk(BIOS_SPEW, "capping to 800/600/400/200 MHz\r\n");
+ printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\n", pos, freq_cap);
+ //printk(BIOS_SPEW, "capping to 800/600/400/200 MHz\n");
//freq_cap &= 0x3f;
return freq_cap;
}
@@ -220,14 +220,14 @@ static int ht_optimize_link(
int needs_reset;
/* Set link width and frequency */
- printk(BIOS_SPEW, "entering ht_optimize_link\r\n");
+ printk(BIOS_SPEW, "entering ht_optimize_link\n");
/* Initially assume everything is already optimized and I don't need a reset */
needs_reset = 0;
/* Get the frequency capabilities */
freq_cap1 = ht_read_freq_cap(dev1, pos1 + LINK_FREQ_CAP(offs1));
freq_cap2 = ht_read_freq_cap(dev2, pos2 + LINK_FREQ_CAP(offs2));
- printk(BIOS_SPEW, "freq_cap1=0x%x, freq_cap2=0x%x\r\n", freq_cap1, freq_cap2);
+ printk(BIOS_SPEW, "freq_cap1=0x%x, freq_cap2=0x%x\n", freq_cap1, freq_cap2);
/* Calculate the highest possible frequency */
freq = log2(freq_cap1 & freq_cap2);
@@ -236,11 +236,11 @@ static int ht_optimize_link(
old_freq = pci_read_config8(dev1, pos1 + LINK_FREQ(offs1));
old_freq &= 0x0f;
needs_reset |= old_freq != freq;
- printk(BIOS_SPEW, "dev1 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\r\n", old_freq, freq, needs_reset);
+ printk(BIOS_SPEW, "dev1 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\n", old_freq, freq, needs_reset);
old_freq = pci_read_config8(dev2, pos2 + LINK_FREQ(offs2));
old_freq &= 0x0f;
needs_reset |= old_freq != freq;
- printk(BIOS_SPEW, "dev2 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\r\n", old_freq, freq, needs_reset);
+ printk(BIOS_SPEW, "dev2 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\n", old_freq, freq, needs_reset);
/* Set the Calculated link frequency */
pci_write_config8(dev1, pos1 + LINK_FREQ(offs1), freq);
@@ -249,45 +249,45 @@ static int ht_optimize_link(
/* Get the width capabilities */
width_cap1 = ht_read_width_cap(dev1, pos1 + LINK_WIDTH(offs1));
width_cap2 = ht_read_width_cap(dev2, pos2 + LINK_WIDTH(offs2));
- printk(BIOS_SPEW, "width_cap1=0x%x, width_cap2=0x%x\r\n", width_cap1, width_cap2);
+ printk(BIOS_SPEW, "width_cap1=0x%x, width_cap2=0x%x\n", width_cap1, width_cap2);
/* Calculate dev1's input width */
ln_width1 = link_width_to_pow2[width_cap1 & 7];
ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7];
- printk(BIOS_SPEW, "dev1 input ln_width1=0x%x, ln_width2=0x%x\r\n", ln_width1, ln_width2);
+ printk(BIOS_SPEW, "dev1 input ln_width1=0x%x, ln_width2=0x%x\n", ln_width1, ln_width2);
if (ln_width1 > ln_width2) {
ln_width1 = ln_width2;
}
width = pow2_to_link_width[ln_width1];
- printk(BIOS_SPEW, "dev1 input width=0x%x\r\n", width);
+ printk(BIOS_SPEW, "dev1 input width=0x%x\n", width);
/* Calculate dev1's output width */
ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7];
ln_width2 = link_width_to_pow2[width_cap2 & 7];
- printk(BIOS_SPEW, "dev1 output ln_width1=0x%x, ln_width2=0x%x\r\n", ln_width1, ln_width2);
+ printk(BIOS_SPEW, "dev1 output ln_width1=0x%x, ln_width2=0x%x\n", ln_width1, ln_width2);
if (ln_width1 > ln_width2) {
ln_width1 = ln_width2;
}
width |= pow2_to_link_width[ln_width1] << 4;
- printk(BIOS_SPEW, "dev1 input|output width=0x%x\r\n", width);
+ printk(BIOS_SPEW, "dev1 input|output width=0x%x\n", width);
/* See if I am changing dev1's width */
old_width = pci_read_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1);
old_width &= 0x77;
needs_reset |= old_width != width;
- printk(BIOS_SPEW, "old dev1 input|output width=0x%x\r\n", width);
+ printk(BIOS_SPEW, "old dev1 input|output width=0x%x\n", width);
/* Set dev1's widths */
pci_write_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1, width);
/* Calculate dev2's width */
width = ((width & 0x70) >> 4) | ((width & 0x7) << 4);
- printk(BIOS_SPEW, "dev2 input|output width=0x%x\r\n", width);
+ printk(BIOS_SPEW, "dev2 input|output width=0x%x\n", width);
/* See if I am changing dev2's width */
old_width = pci_read_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1);
old_width &= 0x77;
needs_reset |= old_width != width;
- printk(BIOS_SPEW, "old dev2 input|output width=0x%x\r\n", width);
+ printk(BIOS_SPEW, "old dev2 input|output width=0x%x\n", width);
/* Set dev2's widths */
pci_write_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1, width);
@@ -371,7 +371,7 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of
print_err("udev="); print_err_hex32(udev);
print_err("\tupos="); print_err_hex32(upos);
print_err("\tuoffs="); print_err_hex32(uoffs);
- print_err("\tHT link capability not found\r\n");
+ print_err("\tHT link capability not found\n");
break;
}
@@ -852,16 +852,16 @@ static int optimize_link_incoherent_ht(struct sys_info *sysinfo)
unsigned link_pair_num = sysinfo->link_pair_num;
- printk(BIOS_SPEW, "entering optimize_link_incoherent_ht\r\n");
- printk(BIOS_SPEW, "sysinfo->link_pair_num=0x%x\r\n", link_pair_num);
+ printk(BIOS_SPEW, "entering optimize_link_incoherent_ht\n");
+ printk(BIOS_SPEW, "sysinfo->link_pair_num=0x%x\n", link_pair_num);
for(i=0; i< link_pair_num; i++) {
struct link_pair_st *link_pair= &sysinfo->link_pair[i];
reset_needed |= ht_optimize_link(link_pair->udev, link_pair->upos, link_pair->uoffs, link_pair->dev, link_pair->pos, link_pair->offs);
- printk(BIOS_SPEW, "after ht_optimize_link for link pair %d, reset_needed=0x%x\r\n", i, reset_needed);
+ printk(BIOS_SPEW, "after ht_optimize_link for link pair %d, reset_needed=0x%x\n", i, reset_needed);
}
reset_needed |= optimize_link_read_pointers_chain(sysinfo->ht_c_num);
- printk(BIOS_SPEW, "after optimize_link_read_pointers_chain, reset_needed=0x%x\r\n", reset_needed);
+ printk(BIOS_SPEW, "after optimize_link_read_pointers_chain, reset_needed=0x%x\n", reset_needed);
return reset_needed;
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index 5500ce65a7..3d853378d8 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -1224,7 +1224,7 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
e0_later_single_core = 0;
}
if(e0_later_single_core) {
- printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\r\n");
+ printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\n");
j=1;
}
diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index 55cdcaf703..4e402e6d7a 100644
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -25,7 +25,7 @@ static inline void print_debug_dqs(const char *str, unsigned val, unsigned level
{
#if DQS_TRAIN_DEBUG > 0
if(DQS_TRAIN_DEBUG > level) {
- printk(BIOS_DEBUG, "%s%x\r\n", str, val);
+ printk(BIOS_DEBUG, "%s%x\n", str, val);
}
#endif
}
@@ -34,7 +34,7 @@ static inline void print_debug_dqs_pair(const char *str, unsigned val, const cha
{
#if DQS_TRAIN_DEBUG > 0
if(DQS_TRAIN_DEBUG > level) {
- printk(BIOS_DEBUG, "%s%08x%s%08x\r\n", str, val, str2, val2);
+ printk(BIOS_DEBUG, "%s%08x%s%08x\n", str, val, str2, val2);
}
#endif
}
@@ -43,14 +43,14 @@ static inline void print_debug_dqs_tsc(const char *str, unsigned i, unsigned val
{
#if DQS_TRAIN_DEBUG > 0
if(DQS_TRAIN_DEBUG > level) {
- printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\r\n", str, i, val, val2);
+ printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\n", str, i, val, val2);
}
#endif
}
static inline void print_debug_dqs_tsc_x(const char *str, unsigned i, unsigned val, unsigned val2)
{
- printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\r\n", str, i, val, val2);
+ printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\n", str, i, val, val2);
}
@@ -583,7 +583,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st
}
}
- print_debug_dqs("\r\nTrainRcvEn: 0 ctrl", ctrl->node_id, 0);
+ print_debug_dqs("\nTrainRcvEn: 0 ctrl", ctrl->node_id, 0);
print_debug_addr("TrainRcvEn: buf_a:", buf_a);
@@ -1401,7 +1401,7 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in
}
- print_debug_dqs("\r\nTrainDQSRdWrPos: 0 ctrl ", ctrl->node_id, 0);
+ print_debug_dqs("\nTrainDQSRdWrPos: 0 ctrl ", ctrl->node_id, 0);
printk(BIOS_DEBUG, "TrainDQSRdWrPos: buf_a:%p\n", buf_a);
@@ -1525,25 +1525,25 @@ static void SetEccDQSRdWrPos(const struct mem_controller *ctrl, struct sys_info
static unsigned train_DqsRcvrEn(const struct mem_controller *ctrl, unsigned Pass, struct sys_info *sysinfo)
{
- print_debug_dqs("\r\ntrain_DqsRcvrEn: begin ctrl ", ctrl->node_id, 0);
+ print_debug_dqs("\ntrain_DqsRcvrEn: begin ctrl ", ctrl->node_id, 0);
if(TrainRcvrEn(ctrl, Pass, sysinfo)) {
return 1;
}
- print_debug_dqs("\r\ntrain_DqsRcvrEn: end ctrl ", ctrl->node_id, 0);
+ print_debug_dqs("\ntrain_DqsRcvrEn: end ctrl ", ctrl->node_id, 0);
return 0;
}
static unsigned train_DqsPos(const struct mem_controller *ctrl, struct sys_info *sysinfo)
{
- print_debug_dqs("\r\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0);
+ print_debug_dqs("\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0);
if(TrainDQSRdWrPos(ctrl, sysinfo) != 0) {
- printk(BIOS_ERR, "\r\nDQS Training Rd Wr failed ctrl%02x\r\n", ctrl->node_id);
+ printk(BIOS_ERR, "\nDQS Training Rd Wr failed ctrl%02x\n", ctrl->node_id);
return 1;
}
else {
SetEccDQSRdWrPos(ctrl, sysinfo);
}
- print_debug_dqs("\r\ntrain_DqsPos: end ctrl ", ctrl->node_id, 0);
+ print_debug_dqs("\ntrain_DqsPos: end ctrl ", ctrl->node_id, 0);
return 0;
}
@@ -1700,7 +1700,7 @@ static unsigned int range_to_mtrr(unsigned int reg,
}
sizek = 1 << align;
#if CONFIG_MEM_TRAIN_SEQ != 1
- printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\r\n",
+ printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n",
reg, range_startk >>10, sizek >> 10,
(type==MTRR_TYPE_UNCACHEABLE)?"UC":
((type==MTRR_TYPE_WRBACK)?"WB":"Other")
@@ -1952,7 +1952,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc
printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass1: %02x\n", i);
if(train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out;
- printk(BIOS_DEBUG, " done\r\n");
+ printk(BIOS_DEBUG, " done\n");
}
tsc[1] = rdtsc();
@@ -1970,7 +1970,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc
printk(BIOS_DEBUG, "DQS Training:DQSPos: %02x\n", i);
if(train_DqsPos(ctrl+i, sysinfo)) goto out;
- printk(BIOS_DEBUG, " done\r\n");
+ printk(BIOS_DEBUG, " done\n");
}
tsc[3] = rdtsc();
@@ -1983,7 +1983,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc
printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass2: %02x\n", i);
if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out;
- printk(BIOS_DEBUG, " done\r\n");
+ printk(BIOS_DEBUG, " done\n");
sysinfo->mem_trained[i]=1;
dqs_save_MC_NVRAM((ctrl+i)->f2);
}
@@ -2033,7 +2033,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info
}
if(v) {
- printk(BIOS_DEBUG, " done\r\n");
+ printk(BIOS_DEBUG, " done\n");
tsc[1] = rdtsc();
printk(BIOS_DEBUG, "set DQS timing:DQSPos: %02x\n", i);
}
@@ -2044,7 +2044,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info
}
if(v) {
- printk(BIOS_DEBUG, " done\r\n");
+ printk(BIOS_DEBUG, " done\n");
tsc[2] = rdtsc();
printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass2: %02x\n", i);
@@ -2055,7 +2055,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info
}
if(v) {
- printk(BIOS_DEBUG, " done\r\n");
+ printk(BIOS_DEBUG, " done\n");
tsc[3] = rdtsc();
}
diff --git a/src/northbridge/amd/amdk8/raminit_test.c b/src/northbridge/amd/amdk8/raminit_test.c
index 329c1afb83..5700c522a2 100644
--- a/src/northbridge/amd/amdk8/raminit_test.c
+++ b/src/northbridge/amd/amdk8/raminit_test.c
@@ -394,7 +394,7 @@ static void test1(void)
#if 0
print_debug("spd_count: ");
print_debug_hex32(spd_count);
- print_debug("\r\n");
+ print_debug("\n");
#endif
}
@@ -410,9 +410,9 @@ static void do_test2(int i)
reset_tests();
spd_fail_count = i;
- print_debug("\r\nSPD will fail after: ");
+ print_debug("\nSPD will fail after: ");
print_debug_hex32(spd_fail_count);
- print_debug(" accesses.\r\n");
+ print_debug(" accesses.\n");
memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256);
memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256);
diff --git a/src/northbridge/amd/amdk8/setup_resource_map.c b/src/northbridge/amd/amdk8/setup_resource_map.c
index cd7b3b54b4..ec3c0cf919 100644
--- a/src/northbridge/amd/amdk8/setup_resource_map.c
+++ b/src/northbridge/amd/amdk8/setup_resource_map.c
@@ -5,14 +5,14 @@ static void setup_resource_map_offset(const unsigned int *register_values, int m
int i;
// print_debug("setting up resource map offset....");
#if 0
- print_debug("\r\n");
+ print_debug("\n");
#endif
for(i = 0; i < max; i += 3) {
device_t dev;
unsigned where;
unsigned long reg;
#if 0
- prink_debug("%08x <- %08x\r\n", register_values[i] + offset_pci_dev, register_values[i+2]);
+ prink_debug("%08x <- %08x\n", register_values[i] + offset_pci_dev, register_values[i+2]);
#endif
dev = (register_values[i] & ~0xfff) + offset_pci_dev;
where = register_values[i] & 0xfff;
@@ -27,7 +27,7 @@ static void setup_resource_map_offset(const unsigned int *register_values, int m
pci_write_config32(register_values[i], reg);
#endif
}
-// print_debug("done.\r\n");
+// print_debug("done.\n");
}
#define RES_PCI_IO 0x10
@@ -45,11 +45,11 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int
#endif
#if RES_DEBUG
- print_debug("\r\n");
+ print_debug("\n");
#endif
for(i = 0; i < max; i += 4) {
#if RES_DEBUG
- printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\r\n",
+ printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n",
i>>2, register_values[i],
register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0),
register_values[i+2],
@@ -112,7 +112,7 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int
}
#if RES_DEBUG
- print_debug("done.\r\n");
+ print_debug("done.\n");
#endif
}
static void setup_resource_map_x(const unsigned int *register_values, int max)
@@ -125,11 +125,11 @@ static void setup_resource_map_x(const unsigned int *register_values, int max)
#endif
#if RES_DEBUG
- print_debug("\r\n");
+ print_debug("\n");
#endif
for(i = 0; i < max; i += 4) {
#if RES_DEBUG
- printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\r\n",
+ printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n",
i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]);
#endif
switch (register_values[i]) {
@@ -188,7 +188,7 @@ static void setup_resource_map_x(const unsigned int *register_values, int max)
}
#if RES_DEBUG
- print_debug("done.\r\n");
+ print_debug("done.\n");
#endif
}
@@ -223,7 +223,7 @@ static void setup_iob_resource_map(const unsigned int *register_values, int max)
print_debug(" -> ");
reg = inb(where);
print_debug_hex8(reg);
- print_debug("\r\n");
+ print_debug("\n");
#endif
}
}
@@ -262,7 +262,7 @@ static void setup_io_resource_map(const unsigned int *register_values, int max)
print_debug(" -> ");
reg = inl(where);
print_debug_hex32(reg);
- print_debug("\r\n");
+ print_debug("\n");
#endif
}
}
@@ -289,7 +289,7 @@ static void setup_mem_resource_map(const unsigned int *register_values, int max)
print_debug(" RB ");
reg = read32(where);
print_debug_hex32(reg);
- print_debug("\r\n");
+ print_debug("\n");
#endif
}
}
diff --git a/src/northbridge/amd/gx1/raminit.c b/src/northbridge/amd/gx1/raminit.c
index 02ff7fb599..f61a69b4f8 100644
--- a/src/northbridge/amd/gx1/raminit.c
+++ b/src/northbridge/amd/gx1/raminit.c
@@ -143,7 +143,7 @@ int comp_banks;
#if 0
print_debug("MC_BANK_CFG = ");
print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG));
- print_debug("\r\n");
+ print_debug("\n");
#endif
/* retrieve the page size from the MC register */
@@ -152,7 +152,7 @@ int comp_banks;
#if 0
print_debug(" page_size = ");
print_debug_hex32(page_size);
- print_debug("\r\n");
+ print_debug("\n");
#endif
comp_banks = (((getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_COMP_BNK << dimm_shift)) >> dimm_shift) >> 12);
@@ -169,7 +169,7 @@ int comp_banks;
#if 0
print_debug("MC_BANK_CFG = ");
print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG));
- print_debug("\r\n");
+ print_debug("\n");
#endif
return(getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_MOD_BNK << dimm_shift));
}
@@ -181,7 +181,7 @@ int page_size = 0x800; /* Smallest page = 1K * 2 banks */
#if 0
print_debug("MC_BANK_CFG = ");
print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG));
- print_debug("\r\n");
+ print_debug("\n");
#endif
page_size = page_size << (((getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_PG_SZ << dimm_shift)) >> dimm_shift) >> 4);
@@ -189,7 +189,7 @@ int page_size = 0x800; /* Smallest page = 1K * 2 banks */
#if 0
print_debug(" page_size = ");
print_debug_hex32(page_size);
- print_debug("\r\n");
+ print_debug("\n");
#endif
setGX1Mem(0, TEST_DATA1);
@@ -203,7 +203,7 @@ int page_size = 0x800; /* Smallest page = 1K * 2 banks */
#if 0
print_debug("MC_BANK_CFG = ");
print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG));
- print_debug("\r\n");
+ print_debug("\n");
#endif
return(getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_COMP_BNK << dimm_shift));
}
@@ -225,7 +225,7 @@ unsigned int probe_config;
#if 0
print_debug(" Page size Config = ");
print_debug_hex32(page_size_config << dimm_shift);
- print_debug("\r\n");
+ print_debug("\n");
#endif
return(page_size_config << dimm_shift);
}
@@ -257,7 +257,7 @@ unsigned int test;
print_debug("Probing for DIMM");
print_debug_char((dimm_shift >> 4) + 0x30);
- print_debug("\r\n");
+ print_debug("\n");
setGX1Mem(0, TEST_DATA1);
setGX1Mem(0x100, 0);
@@ -269,7 +269,7 @@ unsigned int test;
print_debug(" Found DIMM");
print_debug_char((dimm_shift >> 4) + 0x30);
- print_debug("\r\n");
+ print_debug("\n");
return 1;
}
@@ -285,7 +285,7 @@ static int size_memory(int dimm_shift, unsigned int mem_config)
print_debug(" Page Size: ");
print_debug_hex32(0x400 << ((mem_config & (DIMM_PG_SZ << dimm_shift)) >> (dimm_shift + 4)));
- print_debug("\r\n");
+ print_debug("\n");
/* Now do component banks detection */
@@ -294,7 +294,7 @@ static int size_memory(int dimm_shift, unsigned int mem_config)
print_debug(" Component Banks: ");
print_debug_char((((mem_config & (DIMM_COMP_BNK << dimm_shift)) >> (dimm_shift + 12)) ? 4 : 2) + 0x30);
- print_debug("\r\n");
+ print_debug("\n");
/* Now do module banks */
@@ -303,7 +303,7 @@ static int size_memory(int dimm_shift, unsigned int mem_config)
print_debug(" Module Banks: ");
print_debug_char((((mem_config & (DIMM_MOD_BNK << dimm_shift)) >> (dimm_shift + 14)) ? 2 : 1) + 0x30);
- print_debug("\r\n");
+ print_debug("\n");
mem_config &= (~(DIMM_SZ << dimm_shift));
mem_config |= (size_dimm(dimm_shift));
@@ -311,7 +311,7 @@ static int size_memory(int dimm_shift, unsigned int mem_config)
print_debug(" DIMM size: ");
print_debug_hex32(1 <<
((mem_config & (DIMM_SZ << dimm_shift)) >> (dimm_shift + 8)) + 22);
- print_debug("\r\n");
+ print_debug("\n");
return (mem_config);
}
@@ -320,7 +320,7 @@ static void sdram_init(void)
{
unsigned int mem_config = 0x00700070;
- print_debug("Setting up default parameters for memory\r\n");
+ print_debug("Setting up default parameters for memory\n");
outb(0x70, 0x80);
setGX1Mem(GX_BASE + MC_MEM_CNTRL2, 0x000007d8); /* Disable all CLKS, Shift = 3 */
@@ -335,7 +335,7 @@ unsigned int mem_config = 0x00700070;
enable_dimm();
- print_debug("Sizing memory\r\n");
+ print_debug("Sizing memory\n");
setGX1Mem(GX_BASE + MC_BANK_CFG, 0x00705740);
do_refresh();
@@ -346,7 +346,7 @@ unsigned int mem_config = 0x00700070;
print_debug("MC_BANK_CFG = ");
print_debug_hex32(mem_config);
- print_debug("\r\n");
+ print_debug("\n");
setGX1Mem(GX_BASE + MC_BANK_CFG, mem_config);
enable_dimm();
diff --git a/src/northbridge/amd/gx2/pll_reset.c b/src/northbridge/amd/gx2/pll_reset.c
index 5e6b68ace6..040d7b7a4e 100644
--- a/src/northbridge/amd/gx2/pll_reset.c
+++ b/src/northbridge/amd/gx2/pll_reset.c
@@ -276,11 +276,11 @@ static void pll_reset(void)
msr.lo |= PLLMSRlo1;
wrmsr(GLCP_SYS_RSTPLL, msr);
- print_debug("Reset PLL\n\r");
+ print_debug("Reset PLL\n");
msr.lo |= PLLMSRlo2;
wrmsr(GLCP_SYS_RSTPLL,msr);
- print_debug("should not be here\n\r");
+ print_debug("should not be here\n");
#endif
print_err("shit");
while (1)
@@ -289,7 +289,7 @@ static void pll_reset(void)
if (msr.lo & GLCP_SYS_RSTPLL_SWFLAGS_MASK) {
/* PLL is already set and we are reboot from PLL reset */
- print_debug("reboot from BIOS reset\n\r");
+ print_debug("reboot from BIOS reset\n");
return;
}
@@ -310,11 +310,11 @@ static void pll_reset(void)
msr.lo |= ((0xde << 16) | (1 << 26) | (1 << 24));
wrmsr(0x4c000014, msr);
- print_debug("Reset PLL\n\r");
+ print_debug("Reset PLL\n");
msr.lo |= ((1<<14) |(1<<13) | (1<<0));
wrmsr(0x4c000014,msr);
- print_debug("should not be here\n\r");
+ print_debug("should not be here\n");
}
#endif // #if USE_GOODRICH_VERSION
diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c
index e45d696e35..b1cb1af6b3 100644
--- a/src/northbridge/amd/gx2/raminit.c
+++ b/src/northbridge/amd/gx2/raminit.c
@@ -21,13 +21,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr = rdmsr(0x2000001a);
msr.lo = 0x0101;
wrmsr(0x2000001a, msr);
- //print_debug("sdram_enable step 2\r\n");
+ //print_debug("sdram_enable step 2\n");
/* 3. release CKE mask to enable CKE */
msr = rdmsr(0x2000001d);
msr.lo &= ~(0x03 << 8);
wrmsr(0x2000201d, msr);
- //print_debug("sdram_enable step 3\r\n");
+ //print_debug("sdram_enable step 3\n");
/* 4. set and clear REF_TST 16 times, more shouldn't hurt
* why this is before EMRS and MRS ? */
@@ -38,7 +38,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr.lo &= ~(0x01 << 3);
wrmsr(0x20000018, msr);
}
- //print_debug("sdram_enable step 4\r\n");
+ //print_debug("sdram_enable step 4\n");
/* 5. set refresh interval */
msr = rdmsr(0x20000018);
@@ -50,7 +50,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr.lo &= ~(0x03 << 6);
msr.lo |= (0x00 << 6);
wrmsr(0x20000018, msr);
- //print_debug("sdram_enable step 5\r\n");
+ //print_debug("sdram_enable step 5\n");
/* 6. enable DLL, load Extended Mode Register by set and clear PROG_DRAM */
msr = rdmsr(0x20000018);
@@ -58,7 +58,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
wrmsr(0x20000018, msr);
msr.lo &= ~((0x01 << 28) | 0x01);
wrmsr(0x20000018, msr);
- //print_debug("sdram_enable step 6\r\n");
+ //print_debug("sdram_enable step 6\n");
/* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
* it is documented in LX datasheet */
@@ -68,7 +68,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
wrmsr(0x20000018, msr);
msr.lo &= ~((0x01 << 27) | 0x01);
wrmsr(0x20000018, msr);
- //print_debug("sdram_enable step 7\r\n");
+ //print_debug("sdram_enable step 7\n");
/* 8. load Mode Register by set and clear PROG_DRAM */
msr = rdmsr(0x20000018);
@@ -76,7 +76,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
wrmsr(0x20000018, msr);
msr.lo &= ~0x01;
wrmsr(0x20000018, msr);
- //print_debug("sdram_enable step 8\r\n");
+ //print_debug("sdram_enable step 8\n");
/* wait 200 SDCLKs */
for (i = 0; i < 200; i++)
@@ -107,7 +107,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* make sure there is nothing stale in the cache */
__asm__("wbinvd\n");
- print_debug("RAM DLL lock\r\n");
+ print_debug("RAM DLL lock\n");
/* The RAM dll needs a write to lock on so generate a few dummy writes */
volatile unsigned long *ptr;
for (i=0;i<5;i++) {
diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c
index 45a2c9338c..08c19b48e5 100644
--- a/src/northbridge/amd/lx/pll_reset.c
+++ b/src/northbridge/amd/lx/pll_reset.c
@@ -68,7 +68,7 @@ static void pll_reset(char manualconf)
__asm__ __volatile__("hlt\n");
}
- print_debug("Done pll_reset\r\n");
+ print_debug("Done pll_reset\n");
return;
}
diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
index d22efa61c0..15b5be6ea4 100644
--- a/src/northbridge/amd/lx/raminit.c
+++ b/src/northbridge/amd/lx/raminit.c
@@ -32,12 +32,12 @@ static void banner(const char *s)
/* This is so ugly. */
print_debug("===========================");
print_debug(s);
- print_debug("======================================\r\n");
+ print_debug("======================================\n");
}
void hcf(void)
{
- print_emerg("DIE\r\n");
+ print_emerg("DIE\n");
/* this guarantees we flush the UART fifos (if any) and also
* ensures that things, in general, keep going so no debug output
* is lost
@@ -200,7 +200,7 @@ static void checkDDRMax(void)
/* current speed > max speed? */
if (GeodeLinkSpeed() > speed) {
- print_emerg("DIMM overclocked. Check GeodeLink Speed\r\n");
+ print_emerg("DIMM overclocked. Check GeodeLink Speed\n");
POST_CODE(POST_PLL_MEM_FAIL);
hcf();
}
@@ -340,7 +340,7 @@ static void setCAS(void)
} else if ((casmap0 &= casmap1)) {
spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)];
} else {
- print_emerg("DIMM CAS Latencies not compatible\r\n");
+ print_emerg("DIMM CAS Latencies not compatible\n");
POST_CODE(ERROR_DIFF_DIMMS);
hcf();
}
@@ -532,7 +532,7 @@ static void EnableMTest(void)
msr.lo |= CFCLK_LOWER_TRISTATE_DIS_SET;
wrmsr(MC_CFCLK_DBUG, msr);
- print_info("Enabled MTest for TLA debug\r\n");
+ print_info("Enabled MTest for TLA debug\n");
}
static void sdram_set_registers(const struct mem_controller *ctrl)
@@ -576,7 +576,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
banner("Check DIMM 0");
/* Check DIMM is not Register and not Buffered DIMMs. */
if ((spd_byte != 0xFF) && (spd_byte & 3)) {
- print_emerg("DIMM0 NOT COMPATIBLE\r\n");
+ print_emerg("DIMM0 NOT COMPATIBLE\n");
POST_CODE(ERROR_UNSUPPORTED_DIMM);
hcf();
}
@@ -649,7 +649,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr = rdmsr(MC_CF07_DATA);
if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) ==
((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) {
- print_emerg("No memory in the system\r\n");
+ print_emerg("No memory in the system\n");
POST_CODE(ERROR_NO_DIMMS);
hcf();
}
diff --git a/src/northbridge/intel/e7501/debug.c b/src/northbridge/intel/e7501/debug.c
index c05059be99..e5d3ac8741 100644
--- a/src/northbridge/intel/e7501/debug.c
+++ b/src/northbridge/intel/e7501/debug.c
@@ -27,7 +27,7 @@ static void print_pci_devices(void)
continue;
}
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
}
}
@@ -40,9 +40,9 @@ static void dump_pci_device(unsigned dev)
unsigned char val;
if ((i & 0x0f) == 0) {
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "\r\n%02x:",i);
+ printk(BIOS_DEBUG, "\n%02x:",i);
#else
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(i);
print_debug_char(':');
#endif
@@ -55,7 +55,7 @@ static void dump_pci_device(unsigned dev)
print_debug_hex8(val);
#endif
}
- print_debug("\r\n");
+ print_debug("\n");
}
static void dump_pci_devices(void)
@@ -95,7 +95,7 @@ static void dump_pci_devices_on_bus(unsigned busn)
static void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i < 4; i++) {
unsigned device;
device = ctrl->channel0[i];
@@ -114,9 +114,9 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
unsigned char byte;
if ((j & 0xf) == 0) {
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "\r\n%02x: ", j);
+ printk(BIOS_DEBUG, "\n%02x: ", j);
#else
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
#endif
@@ -133,7 +133,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
print_debug_char(' ');
#endif
}
- print_debug("\r\n");
+ print_debug("\n");
}
device = ctrl->channel1[i];
if (device) {
@@ -151,9 +151,9 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
unsigned char byte;
if ((j & 0xf) == 0) {
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "\r\n%02x: ", j);
+ printk(BIOS_DEBUG, "\n%02x: ", j);
#else
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
#endif
@@ -170,14 +170,14 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
print_debug_char(' ');
#endif
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
static void dump_smbus_registers(void)
{
unsigned device;
- print_debug("\r\n");
+ print_debug("\n");
for(device = 1; device < 0x80; device++) {
int j;
if( smbus_read_byte(device, 0) < 0 ) continue;
@@ -196,9 +196,9 @@ static void dump_smbus_registers(void)
}
if ((j & 0xf) == 0) {
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "\r\n%02x: ",j);
+ printk(BIOS_DEBUG, "\n%02x: ",j);
#else
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
#endif
@@ -211,7 +211,7 @@ static void dump_smbus_registers(void)
print_debug_char(' ');
#endif
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
@@ -220,10 +220,10 @@ static void dump_io_resources(unsigned port)
int i;
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "%04x:\r\n", port);
+ printk(BIOS_DEBUG, "%04x:\n", port);
#else
print_debug_hex16(port);
- print_debug(":\r\n");
+ print_debug(":\n");
#endif
for(i=0;i<256;i++) {
uint8_t val;
@@ -243,7 +243,7 @@ static void dump_io_resources(unsigned port)
print_debug_hex8(val);
#endif
if ((i & 0x0f) == 0x0f) {
- print_debug("\r\n");
+ print_debug("\n");
}
port++;
}
@@ -256,9 +256,9 @@ static void dump_mem(unsigned start, unsigned end)
for(i=start;i<end;i++) {
if((i & 0xf)==0) {
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "\r\n%08x:", i);
+ printk(BIOS_DEBUG, "\n%08x:", i);
#else
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex32(i);
print_debug(":");
#endif
@@ -270,6 +270,6 @@ static void dump_mem(unsigned start, unsigned end)
print_debug_hex8((unsigned char)*((unsigned char *)i));
#endif
}
- print_debug("\r\n");
+ print_debug("\n");
}
#endif
diff --git a/src/northbridge/intel/e7501/raminit.c b/src/northbridge/intel/e7501/raminit.c
index c1866070ff..70a692cd92 100644
--- a/src/northbridge/intel/e7501/raminit.c
+++ b/src/northbridge/intel/e7501/raminit.c
@@ -35,7 +35,7 @@
#endif
#define E7501_SDRAM_MODE (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4)
-#define SPD_ERROR "Error reading SPD info\r\n"
+#define SPD_ERROR "Error reading SPD info\n"
// NOTE: This used to be 0x100000.
// That doesn't work on systems where A20M# is asserted, because
@@ -481,7 +481,7 @@ static void do_delay(void)
static void die_on_spd_error(int spd_return_value)
{
if (spd_return_value < 0)
- die("Error reading SPD info\r\n");
+ die("Error reading SPD info\n");
}
//----------------------------------------------------------------------------------
@@ -522,7 +522,7 @@ static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address)
value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
if (value < 0) goto hw_err;
if (value > 2)
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
if (value == 2) {
pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently
@@ -755,7 +755,7 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
spd_value = spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);
if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n");
+ print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
continue;
}
@@ -780,11 +780,11 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
dimm_mask |= ((1<<i) | (1<<(MAX_DIMM_SOCKETS_PER_CHANNEL + i)));
}
else
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n");
+ print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
#else
switch (bDualChannel) {
case 0:
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n");
+ print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
break;
default:
@@ -873,7 +873,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
RAM_DEBUG_MESSAGE(" Sending RAM command to 0x");
RAM_DEBUG_HEX32(dimm_start_address + e7501_mode_bits);
- RAM_DEBUG_MESSAGE("\r\n");
+ RAM_DEBUG_MESSAGE("\n");
read32(dimm_start_address + e7501_mode_bits);
// Set the start of the next DIMM
@@ -1017,10 +1017,10 @@ static void configure_e7501_ram_addresses(const struct mem_controller *ctrl,
RAM_DEBUG_HEX32(sz.side1);
RAM_DEBUG_MESSAGE(" ");
RAM_DEBUG_HEX32(sz.side2);
- RAM_DEBUG_MESSAGE("\r\n");
+ RAM_DEBUG_MESSAGE("\n");
if (sz.side1 == 0)
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
total_dram_64M_multiple = configure_dimm_row_boundaries(sz, total_dram_64M_multiple, i);
}
@@ -1105,7 +1105,7 @@ static void initialize_ecc(void)
uint8_t byte;
- RAM_DEBUG_MESSAGE("Initializing ECC state...\r\n");
+ RAM_DEBUG_MESSAGE("Initializing ECC state...\n");
/* Initialize ECC bits , use ECC zero mode (new to 7501)*/
pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x06);
pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x07);
@@ -1117,7 +1117,7 @@ static void initialize_ecc(void)
} while ( (byte & 0x08 ) == 0);
pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, byte & 0xfc);
- RAM_DEBUG_MESSAGE("ECC state initialized.\r\n");
+ RAM_DEBUG_MESSAGE("ECC state initialized.\n");
/* Clear the ECC error bits */
pci_write_config8(PCI_DEV(0, 0, 1), DRAM_FERR, 0x03);
@@ -1373,7 +1373,7 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, uint8
}
}
else
- die("No CAS# latencies compatible with all DIMMs!!\r\n");
+ die("No CAS# latencies compatible with all DIMMs!!\n");
pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing);
@@ -1462,14 +1462,14 @@ static void configure_e7501_dram_controller_mode(const struct mem_controller *ct
die_on_spd_error(value);
value &= 0x7f; // Mask off self-refresh bit
if(value > MAX_SPD_REFRESH_RATE) {
- print_err("unsupported refresh rate\r\n");
+ print_err("unsupported refresh rate\n");
continue;
}
// Get the appropriate E7501 refresh mode for this DIMM
dimm_refresh_mode = refresh_rate_map[value];
if (dimm_refresh_mode > 7) {
- print_err("unsupported refresh rate\r\n");
+ print_err("unsupported refresh rate\n");
continue;
}
@@ -1680,7 +1680,7 @@ static void ram_set_rcomp_regs(void)
uint32_t dword;
uint8_t maybe_strength_control;
- RAM_DEBUG_MESSAGE("Setting RCOMP registers.\r\n");
+ RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n");
/*enable access to the rcomp bar*/
dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST);
@@ -1805,8 +1805,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
return;
/* 1 & 2 Power up and start clocks */
- RAM_DEBUG_MESSAGE("Ram Enable 1\r\n");
- RAM_DEBUG_MESSAGE("Ram Enable 2\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 1\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 2\n");
/* A 200us delay is needed */
@@ -1814,23 +1814,23 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
EXTRA_DELAY
/* 3. Apply NOP */
- RAM_DEBUG_MESSAGE("Ram Enable 3\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 3\n");
do_ram_command(RAM_COMMAND_NOP, 0);
EXTRA_DELAY
/* 4 Precharge all */
- RAM_DEBUG_MESSAGE("Ram Enable 4\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 4\n");
do_ram_command(RAM_COMMAND_PRECHARGE, 0);
EXTRA_DELAY
/* wait until the all banks idle state... */
/* 5. Issue EMRS to enable DLL */
- RAM_DEBUG_MESSAGE("Ram Enable 5\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 5\n");
do_ram_command(RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE | SDRAM_EXTMODE_DRIVE_NORMAL);
EXTRA_DELAY
/* 6. Reset DLL */
- RAM_DEBUG_MESSAGE("Ram Enable 6\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 6\n");
set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET);
EXTRA_DELAY
@@ -1842,12 +1842,12 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
EXTRA_DELAY
/* 7 Precharge all */
- RAM_DEBUG_MESSAGE("Ram Enable 7\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 7\n");
do_ram_command(RAM_COMMAND_PRECHARGE, 0);
EXTRA_DELAY
/* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */
- RAM_DEBUG_MESSAGE("Ram Enable 8\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 8\n");
do_ram_command(RAM_COMMAND_CBR, 0);
EXTRA_DELAY
do_ram_command(RAM_COMMAND_CBR, 0);
@@ -1867,17 +1867,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
EXTRA_DELAY
/* 9 mode register set */
- RAM_DEBUG_MESSAGE("Ram Enable 9\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 9\n");
set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL);
EXTRA_DELAY
/* 10 DDR Receive FIFO RE-Sync */
- RAM_DEBUG_MESSAGE("Ram Enable 10\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 10\n");
RAM_RESET_DDR_PTR();
EXTRA_DELAY
/* 11 normal operation */
- RAM_DEBUG_MESSAGE("Ram Enable 11\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 11\n");
do_ram_command(RAM_COMMAND_NORMAL, 0);
EXTRA_DELAY
@@ -1897,7 +1897,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
dram_controller_mode |= (1<<17); // NOTE: undocumented reserved bit
pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
- RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\r\n");
+ RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n");
DUMPNORTH();
// verify_ram();
@@ -1917,19 +1917,19 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
{
uint8_t dimm_mask;
- RAM_DEBUG_MESSAGE("Reading SPD data...\r\n");
+ RAM_DEBUG_MESSAGE("Reading SPD data...\n");
//activate_spd_rom(ctrl); Not necessary for this chipset
dimm_mask = spd_get_supported_dimms(ctrl);
if (dimm_mask == 0) {
- print_debug("No usable memory for this controller\r\n");
+ print_debug("No usable memory for this controller\n");
} else {
enable_e7501_clocks(dimm_mask);
- RAM_DEBUG_MESSAGE("setting based on SPD data...\r\n");
+ RAM_DEBUG_MESSAGE("setting based on SPD data...\n");
configure_e7501_row_attributes(ctrl, dimm_mask);
configure_e7501_dram_controller_mode(ctrl, dimm_mask);
@@ -1938,7 +1938,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
configure_e7501_dram_timing(ctrl, dimm_mask);
DO_DELAY
- RAM_DEBUG_MESSAGE("done\r\n");
+ RAM_DEBUG_MESSAGE("done\n");
}
// NOTE: configure_e7501_ram_addresses() is NOT called here.
@@ -1963,7 +1963,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
//
static void sdram_set_registers(const struct mem_controller *ctrl)
{
- RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\r\n");
+ RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n");
DUMPNORTH();
ram_set_rcomp_regs();
diff --git a/src/northbridge/intel/e7520/memory_initialized.c b/src/northbridge/intel/e7520/memory_initialized.c
index 3b9b696a21..133d1c4f88 100644
--- a/src/northbridge/intel/e7520/memory_initialized.c
+++ b/src/northbridge/intel/e7520/memory_initialized.c
@@ -7,7 +7,7 @@ static inline int memory_initialized(void)
drc = pci_read_config32(NB_DEV, DRC);
//print_debug("memory_initialized: DRC: ");
//print_debug_hex32(drc);
- //print_debug("\r\n");
+ //print_debug("\n");
return (drc & (1<<29));
}
diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c
index 3965addcb2..836e6f8c7c 100644
--- a/src/northbridge/intel/e7520/raminit.c
+++ b/src/northbridge/intel/e7520/raminit.c
@@ -74,7 +74,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
reg |= register_values[i+2];
pci_write_config32(dev, where, reg);
}
- print_spew("done.\r\n");
+ print_spew("done.\n");
}
@@ -155,7 +155,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device)
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
sz.side1 = 0;
@@ -283,7 +283,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
dra = 0;
@@ -538,7 +538,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
}
else {
- die("Invalid SPD 9 bus speed.\r\n");
+ die("Invalid SPD 9 bus speed.\n");
}
/* 0x78 DRT */
@@ -576,7 +576,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
ecc = 2;
}
else if (ecc == 1) {
- die("ERROR - Mixed DDR & DDR2 RAM\r\n");
+ die("ERROR - Mixed DDR & DDR2 RAM\n");
}
}
else if ( reg == 7 ) {
@@ -584,15 +584,15 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
ecc = 1;
}
else if ( ecc > 1 ) {
- die("ERROR - Mixed DDR & DDR2 RAM\r\n");
+ die("ERROR - Mixed DDR & DDR2 RAM\n");
}
}
else {
- die("ERROR - RAM not DDR\r\n");
+ die("ERROR - RAM not DDR\n");
}
}
else {
- die("ERROR - Non ECC memory dimm\r\n");
+ die("ERROR - Non ECC memory dimm\n");
}
value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/
@@ -621,10 +621,10 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
ecc = 2;
if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) {
ecc = 0; /* ECC off in CMOS so disable it */
- print_debug("ECC off\r\n");
+ print_debug("ECC off\n");
}
else {
- print_debug("ECC on\r\n");
+ print_debug("ECC on\n");
}
drc &= ~(3 << 20); /* clear the ecc bits */
drc |= (ecc << 20); /* or in the calculated ecc bits */
@@ -654,7 +654,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
drc = 0;
@@ -669,7 +669,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
/* Test if we can read the spd and if ram is ddr or ddr2 */
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
- print_err("No memory for this cpu\r\n");
+ print_err("No memory for this cpu\n");
return;
}
return;
@@ -771,12 +771,12 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
data32 = 0x777becdc; /* ESSD */
break;
}
- die("Error - First dimm slot empty\r\n");
+ die("Error - First dimm slot empty\n");
}
print_debug("ODT Value = ");
print_debug_hex32(data32);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config32(PCI_DEV(0, 0x00, 0), 0xb0, data32);
@@ -1009,7 +1009,7 @@ static void set_receive_enable(const struct mem_controller *ctrl)
print_debug_hex32(recena);
print_debug(", Receive enable B = ");
print_debug_hex32(recenb);
- print_debug("\r\n");
+ print_debug("\n");
/* clear out the calibration area */
write32(BAR+DCALDATA+(16*4), 0x00000000);
@@ -1075,7 +1075,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
0xffffffff, 0xffffffff, 0x000000ff};
mask = spd_detect_dimms(ctrl);
- print_debug("Starting SDRAM Enable\r\n");
+ print_debug("Starting SDRAM Enable\n");
/* 0x80 */
#ifdef DIMM_MAP_LOGICAL
@@ -1087,7 +1087,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* set dram type and Front Side Bus freq. */
drc = spd_set_dram_controller_mode(ctrl, mask);
if( drc == 0) {
- die("Error calculating DRC\r\n");
+ die("Error calculating DRC\n");
}
pll_setup(drc);
data32 = drc & ~(3 << 20); /* clear ECC mode */
@@ -1124,7 +1124,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for(i=0;i<8;i++) { /* loop throught each dimm to test for row */
print_debug("DIMM ");
print_debug_hex8(i);
- print_debug("\r\n");
+ print_debug("\n");
/* Apply NOP */
do_delay();
@@ -1307,7 +1307,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
write32(BAR+DCALCSR, 0x0008000f);
/* clear memory and init ECC */
- print_debug("Clearing memory\r\n");
+ print_debug("Clearing memory\n");
for(i=0;i<64;i+=4) {
write32(BAR+DCALDATA+i, 0x00000000);
}
@@ -1324,13 +1324,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
data32 |= (1 << 31);
pci_write_config32(PCI_DEV(0, 0x00, 0), 0x98, data32);
/* wait for completion */
- print_debug("Waiting for mem complete\r\n");
+ print_debug("Waiting for mem complete\n");
while(1) {
data32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0x98);
if( (data32 & (1<<31)) == 0)
break;
}
- print_debug("Done\r\n");
+ print_debug("Done\n");
/* Set initialization complete */
/* 0x7c DRC */
diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c
index 4aaa26480d..0d18022020 100644
--- a/src/northbridge/intel/e7525/raminit.c
+++ b/src/northbridge/intel/e7525/raminit.c
@@ -74,7 +74,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
reg |= register_values[i+2];
pci_write_config32(dev, where, reg);
}
- print_spew("done.\r\n");
+ print_spew("done.\n");
}
@@ -155,7 +155,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device)
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
sz.side1 = 0;
@@ -283,7 +283,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
dra = 0;
@@ -538,7 +538,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
}
else {
- die("Invalid SPD 9 bus speed.\r\n");
+ die("Invalid SPD 9 bus speed.\n");
}
/* 0x78 DRT */
@@ -576,7 +576,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
ecc = 2;
}
else if (ecc == 1) {
- die("ERROR - Mixed DDR & DDR2 RAM\r\n");
+ die("ERROR - Mixed DDR & DDR2 RAM\n");
}
}
else if ( reg == 7 ) {
@@ -584,15 +584,15 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
ecc = 1;
}
else if ( ecc > 1 ) {
- die("ERROR - Mixed DDR & DDR2 RAM\r\n");
+ die("ERROR - Mixed DDR & DDR2 RAM\n");
}
}
else {
- die("ERROR - RAM not DDR\r\n");
+ die("ERROR - RAM not DDR\n");
}
}
else {
- die("ERROR - Non ECC memory dimm\r\n");
+ die("ERROR - Non ECC memory dimm\n");
}
value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/
@@ -621,10 +621,10 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
ecc = 2;
if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) {
ecc = 0; /* ECC off in CMOS so disable it */
- print_debug("ECC off\r\n");
+ print_debug("ECC off\n");
}
else {
- print_debug("ECC on\r\n");
+ print_debug("ECC on\n");
}
drc &= ~(3 << 20); /* clear the ecc bits */
drc |= (ecc << 20); /* or in the calculated ecc bits */
@@ -654,7 +654,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
drc = 0;
@@ -669,7 +669,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
/* Test if we can read the spd and if ram is ddr or ddr2 */
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
- print_err("No memory for this cpu\r\n");
+ print_err("No memory for this cpu\n");
return;
}
return;
@@ -742,12 +742,12 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
data32 = 0x777becdc; /* ESSD */
break;
}
- die("Error - First dimm slot empty\r\n");
+ die("Error - First dimm slot empty\n");
}
print_debug("ODT Value = ");
print_debug_hex32(data32);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config32(ctrl->f0, 0xb0, data32);
@@ -980,7 +980,7 @@ static void set_receive_enable(const struct mem_controller *ctrl)
print_debug_hex32(recena);
print_debug(", Receive enable B = ");
print_debug_hex32(recenb);
- print_debug("\r\n");
+ print_debug("\n");
/* clear out the calibration area */
write32(BAR+DCALDATA+(16*4), 0x00000000);
@@ -1046,7 +1046,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
0xffffffff, 0xffffffff, 0x000000ff};
mask = spd_detect_dimms(ctrl);
- print_debug("Starting SDRAM Enable\r\n");
+ print_debug("Starting SDRAM Enable\n");
/* 0x80 */
#ifdef DIMM_MAP_LOGICAL
@@ -1058,7 +1058,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* set dram type and Front Side Bus freq. */
drc = spd_set_dram_controller_mode(ctrl, mask);
if( drc == 0) {
- die("Error calculating DRC\r\n");
+ die("Error calculating DRC\n");
}
data32 = drc & ~(3 << 20); /* clear ECC mode */
data32 = data32 & ~(7 << 8); /* clear refresh rates */
@@ -1094,7 +1094,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for(i=0;i<8;i++) { /* loop throught each dimm to test for row */
print_debug("DIMM ");
print_debug_hex8(i);
- print_debug("\r\n");
+ print_debug("\n");
/* Apply NOP */
do_delay();
@@ -1274,7 +1274,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
write32(BAR+DCALCSR, 0x0008000f);
/* clear memory and init ECC */
- print_debug("Clearing memory\r\n");
+ print_debug("Clearing memory\n");
for(i=0;i<64;i+=4) {
write32(BAR+DCALDATA+i, 0x00000000);
}
@@ -1291,13 +1291,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
data32 |= (1 << 31);
pci_write_config32(ctrl->f0, 0x98, data32);
/* wait for completion */
- print_debug("Waiting for mem complete\r\n");
+ print_debug("Waiting for mem complete\n");
while(1) {
data32 = pci_read_config32(ctrl->f0, 0x98);
if( (data32 & (1<<31)) == 0)
break;
}
- print_debug("Done\r\n");
+ print_debug("Done\n");
/* Set initialization complete */
/* 0x7c DRC */
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 76475ce235..fa44d599f1 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -76,7 +76,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
reg |= register_values[i+2];
pci_write_config32(dev, where, reg);
}
- print_spew("done.\r\n");
+ print_spew("done.\n");
}
struct dimm_size {
@@ -149,7 +149,7 @@ static struct dimm_size spd_get_dimm_size(u16 device)
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
sz.side1 = 0;
@@ -277,7 +277,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
dra = 0;
@@ -528,7 +528,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
}
else {
- die("Invalid SPD 9 bus speed.\r\n");
+ die("Invalid SPD 9 bus speed.\n");
}
/* 0x78 DRT */
@@ -556,7 +556,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
continue;
}
value = spd_read_byte(ctrl->channel0[cnt], 11); /* ECC */
- if (value != 2) die("ERROR - Non ECC memory dimm\r\n");
+ if (value != 2) die("ERROR - Non ECC memory dimm\n");
value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/
value &= 0x0f; /* clip self refresh bit */
@@ -595,7 +595,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
drc = 0;
@@ -610,7 +610,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
/* Test if we can read the spd and if ram is ddr or ddr2 */
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
- print_err("No memory for this cpu\r\n");
+ print_err("No memory for this cpu\n");
return;
}
return;
@@ -683,12 +683,12 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
data32 = 0x777becdc; /* ESSD */
break;
}
- die("Error - First dimm slot empty\r\n");
+ die("Error - First dimm slot empty\n");
}
print_debug("ODT Value = ");
print_debug_hex32(data32);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config32(ctrl->f0, DDR2ODTC, data32);
@@ -921,7 +921,7 @@ static void set_receive_enable(const struct mem_controller *ctrl)
print_debug_hex32(recena);
print_debug(", Receive enable B = ");
print_debug_hex32(recenb);
- print_debug("\r\n");
+ print_debug("\n");
/* clear out the calibration area */
write32(MCBAR+DCALDATA+(16*4), 0x00000000);
@@ -977,7 +977,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
0xffffffff, 0xffffffff, 0x000000ff};
mask = spd_detect_dimms(ctrl);
- print_debug("Starting SDRAM Enable\r\n");
+ print_debug("Starting SDRAM Enable\n");
/* 0x80 */
#ifdef DIMM_MAP_LOGICAL
@@ -989,7 +989,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* set dram type and Front Side Bus freq. */
drc = spd_set_dram_controller_mode(ctrl, mask);
if( drc == 0) {
- die("Error calculating DRC\r\n");
+ die("Error calculating DRC\n");
}
data32 = drc & ~(3 << 20); /* clear ECC mode */
data32 = data32 & ~(7 << 8); /* clear refresh rates */
@@ -1024,7 +1024,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for(i=0;i<8;i+=2) { /* loop through each dimm to test */
print_debug("DIMM ");
print_debug_hex8(i);
- print_debug("\r\n");
+ print_debug("\n");
/* Apply NOP */
do_delay();
@@ -1177,7 +1177,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
write32(MCBAR+DCALCSR, 0x0008000f);
/* clear memory and init ECC */
- print_debug("Clearing memory\r\n");
+ print_debug("Clearing memory\n");
for(i=0;i<64;i+=4) {
write32(MCBAR+DCALDATA+i, 0x00000000);
}
@@ -1194,13 +1194,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
data32 |= (1 << 31);
pci_write_config32(ctrl->f0, 0x98, data32);
/* wait for completion */
- print_debug("Waiting for mem complete\r\n");
+ print_debug("Waiting for mem complete\n");
while(1) {
data32 = pci_read_config32(ctrl->f0, 0x98);
if( (data32 & (1<<31)) == 0)
break;
}
- print_debug("Done\r\n");
+ print_debug("Done\n");
/* Set initialization complete */
/* 0x7c DRC */
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index 9ad778bf13..5a4a328e44 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -122,7 +122,7 @@ static struct dimm_size spd_get_dimm_size(u16 device)
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
sz.side1 = 0;
@@ -134,7 +134,7 @@ static struct dimm_size spd_get_dimm_size(u16 device)
print_debug_hex8(sz.side1);
print_debug(".");
print_debug_hex8(sz.side2);
- print_debug("\r\n");
+ print_debug("\n");
return sz;
}
@@ -167,14 +167,14 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, u8 dimm_mask)
}
print_debug("DRB = ");
print_debug_hex32(pci_read_config32(ctrl->f0, DRB));
- print_debug("\r\n");
+ print_debug("\n");
cum >>= 1;
/* set TOM top of memory */
pci_write_config16(ctrl->f0, TOM, cum);
print_debug("TOM = ");
print_debug_hex16(cum);
- print_debug("\r\n");
+ print_debug("\n");
/* set TOLM top of low memory */
if (cum > 0x18) {
cum = 0x18;
@@ -183,7 +183,7 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, u8 dimm_mask)
pci_write_config16(ctrl->f0, TOLM, cum);
print_debug("TOLM = ");
print_debug_hex16(cum);
- print_debug("\r\n");
+ print_debug("\n");
return 0;
}
@@ -202,7 +202,7 @@ static u8 spd_detect_dimms(const struct mem_controller *ctrl)
print_debug_hex8(device);
print_debug(" = ");
print_debug_hex8(byte);
- print_debug("\r\n");
+ print_debug("\n");
if (byte == 8) {
dimm_mask |= (1 << i);
}
@@ -227,29 +227,29 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
}
value = spd_read_byte(ctrl->channel0[i], SPD_NUM_ROWS);
- if (value < 0) die("Bad SPD data\r\n");
- if ((value & 0xf) == 0) die("Invalid # of rows\r\n");
+ if (value < 0) die("Bad SPD data\n");
+ if ((value & 0xf) == 0) die("Invalid # of rows\n");
dra |= (((value-13) & 0x7) << 23);
dra |= (((value-13) & 0x7) << 29);
reg += value & 0xf;
value = spd_read_byte(ctrl->channel0[i], SPD_NUM_COLUMNS);
- if (value < 0) die("Bad SPD data\r\n");
- if ((value & 0xf) == 0) die("Invalid # of columns\r\n");
+ if (value < 0) die("Bad SPD data\n");
+ if ((value & 0xf) == 0) die("Invalid # of columns\n");
dra |= (((value-10) & 0x7) << 20);
dra |= (((value-10) & 0x7) << 26);
reg += value & 0xf;
value = spd_read_byte(ctrl->channel0[i], SPD_NUM_BANKS_PER_SDRAM);
- if (value < 0) die("Bad SPD data\r\n");
- if ((value & 0xff) == 0) die("Invalid # of banks\r\n");
+ if (value < 0) die("Bad SPD data\n");
+ if ((value & 0xff) == 0) die("Invalid # of banks\n");
reg += log2(value & 0xff);
print_debug("dimm ");
print_debug_hex8(i);
print_debug(" reg = ");
print_debug_hex8(reg);
- print_debug("\r\n");
+ print_debug("\n");
/* set device density */
dra |= ((31-reg));
@@ -270,7 +270,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
print_debug_hex8(i);
print_debug(" = ");
print_debug_hex32(dra);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config32(ctrl->f0, DRA + (i*4), dra);
}
@@ -320,10 +320,10 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl,
else if (val & 0x40)
cl = 6;
else
- die("CAS latency mismatch\r\n");
+ die("CAS latency mismatch\n");
print_debug("cl = ");
print_debug_hex8(cl);
- print_debug("\r\n");
+ print_debug("\n");
ci = cycle[index];
@@ -349,10 +349,10 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl,
}
print_debug("trc = ");
print_debug_hex8(trc);
- print_debug("\r\n");
+ print_debug("\n");
print_debug("trfc = ");
print_debug_hex8(trfc);
- print_debug("\r\n");
+ print_debug("\n");
/* Tras, Trtp, Twtr in cycles */
for (i = 0; i < DIMM_SOCKETS; i++) {
@@ -374,38 +374,38 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl,
}
print_debug("tras = ");
print_debug_hex8(tras);
- print_debug("\r\n");
+ print_debug("\n");
print_debug("trtp = ");
print_debug_hex8(trtp);
- print_debug("\r\n");
+ print_debug("\n");
print_debug("twtr = ");
print_debug_hex8(twtr);
- print_debug("\r\n");
+ print_debug("\n");
val = (drt0[index] | ((trc - 11) << 12) | ((cl - 3) << 9)
| ((cl - 3) << 6) | ((cl - 3) << 3));
print_debug("drt0 = ");
print_debug_hex32(val);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config32(ctrl->f0, DRT0, val);
val = (drt1[index] | ((tras - 8) << 28) | ((trtp - 2) << 25)
| (twtr << 15));
print_debug("drt1 = ");
print_debug_hex32(val);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config32(ctrl->f0, DRT1, val);
val = (magic[index]);
print_debug("magic = ");
print_debug_hex32(val);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config32(PCI_DEV(0, 0x08, 0), 0xcc, val);
val = (mrs[index] | (cl << 20));
print_debug("mrs = ");
print_debug_hex32(val);
- print_debug("\r\n");
+ print_debug("\n");
return val;
}
@@ -422,11 +422,11 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
if (!(dimm_mask & (1 << i)))
continue;
if ((spd_read_byte(ctrl->channel0[i], SPD_MODULE_DATA_WIDTH_LSB) & 0xf0) != 0x40)
- die("ERROR: Only 64-bit DIMMs supported\r\n");
+ die("ERROR: Only 64-bit DIMMs supported\n");
if (!(spd_read_byte(ctrl->channel0[i], SPD_DIMM_CONFIG_TYPE) & 0x02))
- die("ERROR: Only ECC DIMMs supported\r\n");
+ die("ERROR: Only ECC DIMMs supported\n");
if (spd_read_byte(ctrl->channel0[i], SPD_PRIMARY_SDRAM_WIDTH) != 0x08)
- die("ERROR: Only x8 DIMMs supported\r\n");
+ die("ERROR: Only x8 DIMMs supported\n");
value = spd_read_byte(ctrl->channel0[i], SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
if (value > cycle)
@@ -434,7 +434,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
}
print_debug("cycle = ");
print_debug_hex8(cycle);
- print_debug("\r\n");
+ print_debug("\n");
drc |= (1 << 20); /* enable ECC */
drc |= (3 << 30); /* enable CKE on each DIMM */
@@ -446,42 +446,42 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
print_debug("msr 0xcd = ");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
- print_debug("\r\n");
+ print_debug("\n");
/* TODO check that this msr really indicates fsb speed! */
if (msr.lo & 0x07) {
- print_info("533 MHz FSB\r\n");
+ print_info("533 MHz FSB\n");
if (cycle <= 0x25) {
drc |= 0x5;
- print_info("400 MHz DDR\r\n");
+ print_info("400 MHz DDR\n");
} else if (cycle <= 0x30) {
drc |= 0x7;
- print_info("333 MHz DDR\r\n");
+ print_info("333 MHz DDR\n");
} else if (cycle <= 0x3d) {
drc |= 0x4;
- print_info("266 MHz DDR\r\n");
+ print_info("266 MHz DDR\n");
} else {
drc |= 0x2;
- print_info("200 MHz DDR\r\n");
+ print_info("200 MHz DDR\n");
}
}
else {
- print_info("400 MHz FSB\r\n");
+ print_info("400 MHz FSB\n");
if (cycle <= 0x30) {
drc |= 0x7;
- print_info("333 MHz DDR\r\n");
+ print_info("333 MHz DDR\n");
} else if (cycle <= 0x3d) {
drc |= 0x0;
- print_info("266 MHz DDR\r\n");
+ print_info("266 MHz DDR\n");
} else {
drc |= 0x2;
- print_info("200 MHz DDR\r\n");
+ print_info("200 MHz DDR\n");
}
}
print_debug("DRC = ");
print_debug_hex32(drc);
- print_debug("\r\n");
+ print_debug("\n");
return drc;
}
@@ -494,7 +494,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
/* Test if we can read the SPD */
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
- print_err("No memory for this cpu\r\n");
+ print_err("No memory for this cpu\n");
return;
}
return;
@@ -524,14 +524,14 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
print_debug("ODT Value = ");
print_debug_hex32(data32);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config32(ctrl->f0, DDR2ODTC, data32);
for (i = 0; i < 2; i++) {
print_debug("ODT CS");
print_debug_hex8(i);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALADDR, 0x0b840001);
write32(BAR+DCALCSR, 0x80000003 | ((i+1)<<21));
@@ -547,14 +547,14 @@ static void dump_dcal_regs(void)
int i;
for (i = 0x0; i < 0x2a0; i += 4) {
if ((i % 16) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex16(i);
print_debug(": ");
}
print_debug_hex32(read32(BAR+i));
print_debug(" ");
}
- print_debug("\r\n");
+ print_debug("\n");
}
@@ -570,12 +570,12 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
u16 data16;
mask = spd_detect_dimms(ctrl);
- print_debug("Starting SDRAM Enable\r\n");
+ print_debug("Starting SDRAM Enable\n");
/* Set DRAM type and Front Side Bus frequency */
drc = spd_set_dram_controller_mode(ctrl, mask);
if (drc == 0) {
- die("Error calculating DRC\r\n");
+ die("Error calculating DRC\n");
}
data32 = drc & ~(3 << 20); /* clear ECC mode */
data32 = data32 | (3 << 5); /* temp turn off ODT */
@@ -600,7 +600,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for (cs = 0; cs < 2; cs++) {
print_debug("NOP CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
udelay(16);
write32(BAR+DCALCSR, (0x00000000 | ((cs+1)<<21)));
write32(BAR+DCALCSR, (0x80000000 | ((cs+1)<<21)));
@@ -614,7 +614,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for (cs = 0; cs < 2; cs++) {
print_debug("NOP CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
while (data32 & 0x80000000)
@@ -626,7 +626,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for (cs = 0; cs < 2; cs++) {
print_debug("Precharge CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALADDR, 0x04000000);
write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
@@ -639,7 +639,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for (cs = 0; cs < 2; cs++) {
print_debug("EMRS CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALADDR, 0x0b840001);
write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
@@ -651,7 +651,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for (cs = 0; cs < 2; cs++) {
print_debug("MRS CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALADDR, mode_reg);
write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
@@ -664,7 +664,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for (cs = 0; cs < 2; cs++) {
print_debug("Precharge CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALADDR, 0x04000000);
write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
@@ -678,7 +678,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for (cs = 0; cs < 2; cs++) {
print_debug("Refresh CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
while (data32 & 0x80000000)
@@ -691,7 +691,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for (cs = 0; cs < 2; cs++) {
print_debug("MRS CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
@@ -704,7 +704,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for (cs = 0; cs < 2; cs++) {
print_debug("EMRS CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALADDR, 0x0b840001);
write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
@@ -728,7 +728,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for (cs = 0; cs < 1; cs++) {
print_debug("receive enable calibration CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALCSR, (0x8000000c | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
while (data32 & 0x80000000)
@@ -755,17 +755,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
continue;
print_debug("clear memory CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+MBCSR, 0xa00000f0 | ((cs+1)<<20) | (0<<16));
data32 = read32(BAR+MBCSR);
while (data32 & 0x80000000)
data32 = read32(BAR+MBCSR);
if (data32 & 0x40000000)
- print_debug("failed!\r\n");
+ print_debug("failed!\n");
}
/* Clear read/write FIFO pointers */
- print_debug("clear read/write fifo pointers\r\n");
+ print_debug("clear read/write fifo pointers\n");
write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) | (1<<15));
udelay(16);
write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) & ~(1<<15));
@@ -773,7 +773,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
dump_dcal_regs();
- print_debug("Done\r\n");
+ print_debug("Done\n");
/* Set initialization complete */
drc |= (1 << 29);
diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c
index fab224dc85..b437755213 100644
--- a/src/northbridge/intel/i440bx/debug.c
+++ b/src/northbridge/intel/i440bx/debug.c
@@ -2,7 +2,7 @@
static void dump_spd_registers(void)
{
int i;
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i < DIMM_SOCKETS; i++) {
unsigned device;
device = DIMM_SPD_BASE + i;
@@ -16,20 +16,20 @@ static void dump_spd_registers(void)
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = spd_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index 016bf67f93..789ea82db9 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -420,7 +420,7 @@ static void do_ram_command(u32 command)
PRINT_DEBUG_HEX16(reg16);
PRINT_DEBUG(" to 0x");
PRINT_DEBUG_HEX32(addr);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
read32(addr);
@@ -606,7 +606,7 @@ static void spd_enable_refresh(void)
PRINT_DEBUG_HEX8(reg);
PRINT_DEBUG(") for DIMM ");
PRINT_DEBUG_HEX8(i);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
}
pci_write_config8(NB, DRAMC, reg);
@@ -621,7 +621,7 @@ static void sdram_set_registers(void)
int i, max;
uint8_t reg;
- PRINT_DEBUG("Northbridge prior to SDRAM init:\r\n");
+ PRINT_DEBUG("Northbridge prior to SDRAM init:\n");
DUMPNORTH();
max = ARRAY_SIZE(register_values);
@@ -637,7 +637,7 @@ static void sdram_set_registers(void)
PRINT_DEBUG_HEX8(register_values[i]);
PRINT_DEBUG(" to 0x");
PRINT_DEBUG_HEX8(reg);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
}
}
@@ -731,11 +731,11 @@ static void set_dram_row_attributes(void)
}
PRINT_DEBUG("DIMM in slot ");
PRINT_DEBUG_HEX8(i);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
if (edosd == 0x06) {
- print_err("Mixing EDO/SDRAM unsupported!\r\n");
- die("HALT\r\n");
+ print_err("Mixing EDO/SDRAM unsupported!\n");
+ die("HALT\n");
}
/* "DRA" is our RPS for the two rows on this DIMM. */
@@ -816,12 +816,12 @@ static void set_dram_row_attributes(void)
if (col == 4)
bpr |= 0xc0;
} else {
- print_err("# of banks of DIMM unsupported!\r\n");
- die("HALT\r\n");
+ print_err("# of banks of DIMM unsupported!\n");
+ die("HALT\n");
}
if (dra == -1) {
- print_err("Page size not supported\r\n");
- die("HALT\r\n");
+ print_err("Page size not supported\n");
+ die("HALT\n");
}
/*
@@ -831,14 +831,14 @@ static void set_dram_row_attributes(void)
*/
struct dimm_size sz = spd_get_dimm_size(device);
if ((sz.side1 < 8)) {
- print_err("DIMMs smaller than 8MB per side\r\n"
- "are not supported on this NB.\r\n");
- die("HALT\r\n");
+ print_err("DIMMs smaller than 8MB per side\n"
+ "are not supported on this NB.\n");
+ die("HALT\n");
}
if ((sz.side1 > 128)) {
- print_err("DIMMs > 128MB per side\r\n"
- "are not supported on this NB\r\n");
- die("HALT\r\n");
+ print_err("DIMMs > 128MB per side\n"
+ "are not supported on this NB\n");
+ die("HALT\n");
}
/* Divide size by 8 to set up the DRB registers. */
@@ -855,7 +855,7 @@ static void set_dram_row_attributes(void)
#if 0
PRINT_DEBUG("No DIMM found in slot ");
PRINT_DEBUG_HEX8(i);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
/* If there's no DIMM in the slot, set dra to 0x00. */
@@ -870,7 +870,7 @@ static void set_dram_row_attributes(void)
#if 0
PRINT_DEBUG("DRB has been set to 0x");
PRINT_DEBUG_HEX16(drb);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
/* Brings the upper DRB back down to be base for
@@ -886,19 +886,19 @@ static void set_dram_row_attributes(void)
pci_write_config8(NB, PGPOL + 1, bpr);
PRINT_DEBUG("PGPOL[BPR] has been set to 0x");
PRINT_DEBUG_HEX8(bpr);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
/* Set DRAM row page size register. */
pci_write_config16(NB, RPS, rps);
PRINT_DEBUG("RPS has been set to 0x");
PRINT_DEBUG_HEX16(rps);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
/* ### ECC */
pci_write_config8(NB, NBXCFG + 3, nbxecc);
PRINT_DEBUG("NBXECC[31:24] has been set to 0x");
PRINT_DEBUG_HEX8(nbxecc);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
/* Set DRAMC[4:3] to proper memory type (EDO/SDRAM).
* TODO: Registered SDRAM support.
@@ -917,7 +917,7 @@ static void set_dram_row_attributes(void)
pci_write_config8(NB, DRAMC, value);
PRINT_DEBUG("DRAMC has been set to 0x");
PRINT_DEBUG_HEX8(value);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
}
static void sdram_set_spd_registers(void)
@@ -947,38 +947,38 @@ static void sdram_enable(void)
udelay(200);
/* 1. Apply NOP. Wait 200 clock cycles (200us should do). */
- PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
+ PRINT_DEBUG("RAM Enable 1: Apply NOP\n");
do_ram_command(RAM_COMMAND_NOP);
udelay(200);
/* 2. Precharge all. Wait tRP. */
- PRINT_DEBUG("RAM Enable 2: Precharge all\r\n");
+ PRINT_DEBUG("RAM Enable 2: Precharge all\n");
do_ram_command(RAM_COMMAND_PRECHARGE);
udelay(1);
/* 3. Perform 8 refresh cycles. Wait tRC each time. */
- PRINT_DEBUG("RAM Enable 3: CBR\r\n");
+ PRINT_DEBUG("RAM Enable 3: CBR\n");
for (i = 0; i < 8; i++) {
do_ram_command(RAM_COMMAND_CBR);
udelay(1);
}
/* 4. Mode register set. Wait two memory cycles. */
- PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
+ PRINT_DEBUG("RAM Enable 4: Mode register set\n");
do_ram_command(RAM_COMMAND_MRS);
udelay(2);
/* 5. Normal operation. */
- PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
+ PRINT_DEBUG("RAM Enable 5: Normal operation\n");
do_ram_command(RAM_COMMAND_NORMAL);
udelay(1);
/* 6. Finally enable refresh. */
- PRINT_DEBUG("RAM Enable 6: Enable refresh\r\n");
+ PRINT_DEBUG("RAM Enable 6: Enable refresh\n");
// pci_write_config8(NB, PMCR, 0x10);
spd_enable_refresh();
udelay(1);
- PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
+ PRINT_DEBUG("Northbridge following SDRAM init:\n");
DUMPNORTH();
}
diff --git a/src/northbridge/intel/i440lx/raminit.c b/src/northbridge/intel/i440lx/raminit.c
index 5d07441dde..6259608b48 100644
--- a/src/northbridge/intel/i440lx/raminit.c
+++ b/src/northbridge/intel/i440lx/raminit.c
@@ -171,7 +171,7 @@ static void do_ram_command(u32 command)
PRINT_DEBUG_HEX16(reg16);
PRINT_DEBUG(" to 0x");
PRINT_DEBUG_HEX32(addr);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
read32(addr);
@@ -201,7 +201,7 @@ static void spd_enable_refresh(void)
PRINT_DEBUG("spd_enable_refresh: dramc = 0x");
PRINT_DEBUG_HEX8(reg);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
}
/*-----------------------------------------------------------------------------
@@ -225,7 +225,7 @@ static void northbridge_init(void)
reg32 = pci_read_config32(NB, APBASE);
PRINT_DEBUG("APBASE ");
PRINT_DEBUG_HEX32(reg32);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
}
@@ -244,10 +244,10 @@ static void sdram_set_registers(void)
#if 0
uint16_t reg16;
reg16 = pci_read_config16(NB, PACCFG);
- printk(BIOS_DEBUG, "i82443LX Host Freq: 6%C MHz\r\n", (reg16 & 0x4000) ? '0' : '6');
+ printk(BIOS_DEBUG, "i82443LX Host Freq: 6%C MHz\n", (reg16 & 0x4000) ? '0' : '6');
#endif
- PRINT_DEBUG("Northbridge prior to SDRAM init:\r\n");
+ PRINT_DEBUG("Northbridge prior to SDRAM init:\n");
DUMPNORTH();
northbridge_init();
@@ -279,11 +279,11 @@ static void sdram_set_registers(void)
} else {
PRINT_DEBUG(" FAIL ");
}
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
}
- PRINT_DEBUG("Northbridge atexit sdram set registers\r\n");
+ PRINT_DEBUG("Northbridge atexit sdram set registers\n");
DUMPNORTH();
}
@@ -342,7 +342,7 @@ static void sdram_set_spd_registers(void)
*/
PRINT_DEBUG_HEX16(ds);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
memsize += ds;
@@ -363,7 +363,7 @@ static void sdram_set_spd_registers(void)
PRINT_DEBUG(" ");
PRINT_DEBUG_HEX16(ds);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
/*
* modify DRT register if current row isn't empty
@@ -384,7 +384,7 @@ static void sdram_set_spd_registers(void)
#if 0
PRINT_DEBUG("Mem: 0x");
PRINT_DEBUG_HEX16(memsize * 8);
- PRINT_DEBUG(" MB\r\n");
+ PRINT_DEBUG(" MB\n");
if (memsize == 0) {
/* maybe we should use some nice die/hlt sequence with printing on console
@@ -392,8 +392,8 @@ static void sdram_set_spd_registers(void)
* maybe such event_handler can be commonly defined routine to decrease
* code duplication?
*/
- PRINT_DEBUG("No memory detected via SPD\r\n");
- PRINT_DEBUG("Reverting to hardcoded 64M single side dimm in first bank\r\n");
+ PRINT_DEBUG("No memory detected via SPD\n");
+ PRINT_DEBUG("Reverting to hardcoded 64M single side dimm in first bank\n");
}
#endif
@@ -418,38 +418,38 @@ static void sdram_enable(void)
udelay(200);
/* 1. Apply NOP. Wait 200 clock cycles (clock might be 60 or 66 Mhz). */
- PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
+ PRINT_DEBUG("RAM Enable 1: Apply NOP\n");
do_ram_command(RAM_COMMAND_NOP);
udelay(200);
/* 2. Precharge all. Wait tRP. */
- PRINT_DEBUG("RAM Enable 2: Precharge all\r\n");
+ PRINT_DEBUG("RAM Enable 2: Precharge all\n");
do_ram_command(RAM_COMMAND_PRECHARGE);
udelay(1);
/* 3. Perform 8 refresh cycles. Wait tRC each time. */
- PRINT_DEBUG("RAM Enable 3: CBR\r\n");
+ PRINT_DEBUG("RAM Enable 3: CBR\n");
for (i = 0; i < 8; i++) {
do_ram_command(RAM_COMMAND_CBR);
udelay(1);
}
/* 4. Mode register set. Wait two memory cycles. */
- PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
+ PRINT_DEBUG("RAM Enable 4: Mode register set\n");
do_ram_command(RAM_COMMAND_MRS);
udelay(2);
/* 5. Normal operation. */
- PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
+ PRINT_DEBUG("RAM Enable 5: Normal operation\n");
do_ram_command(RAM_COMMAND_NORMAL);
udelay(1);
/* 6. Finally enable refresh. */
- PRINT_DEBUG("RAM Enable 6: Enable refresh\r\n");
+ PRINT_DEBUG("RAM Enable 6: Enable refresh\n");
pci_write_config8(NB, DRAMC, 0x01);
spd_enable_refresh();
udelay(1);
- PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
+ PRINT_DEBUG("Northbridge following SDRAM init:\n");
}
diff --git a/src/northbridge/intel/i82810/debug.c b/src/northbridge/intel/i82810/debug.c
index 5733700af3..87b039f5f5 100644
--- a/src/northbridge/intel/i82810/debug.c
+++ b/src/northbridge/intel/i82810/debug.c
@@ -2,7 +2,7 @@
static void dump_spd_registers(void)
{
int i;
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i < DIMM_SOCKETS; i++) {
unsigned device;
device = DIMM_SPD_BASE + i;
@@ -16,20 +16,20 @@ static void dump_spd_registers(void)
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c
index e88580c5e8..86602eae34 100644
--- a/src/northbridge/intel/i82810/raminit.c
+++ b/src/northbridge/intel/i82810/raminit.c
@@ -150,7 +150,7 @@ static void do_ram_command(u8 command)
PRINT_DEBUG_HEX8(reg8);
PRINT_DEBUG(" to 0x");
PRINT_DEBUG_HEX32(addr);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
read32(addr);
@@ -164,7 +164,7 @@ static void do_ram_command(u8 command)
PRINT_DEBUG_HEX8(reg8);
PRINT_DEBUG(" to 0x");
PRINT_DEBUG_HEX32(addr);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
read32(addr);
}
@@ -194,14 +194,14 @@ static void spd_set_dram_size(void)
if (smbus_read_byte(DIMM_SPD_BASE + i, 2) == 4) {
print_debug("Found DIMM in slot ");
print_debug_hex8(i);
- print_debug("\r\n");
+ print_debug("\n");
dimm_size = smbus_read_byte(DIMM_SPD_BASE + i, 31);
/* WISHLIST: would be nice to display it as decimal? */
print_debug("DIMM is 0x");
print_debug_hex8(dimm_size * 4);
- print_debug("MB\r\n");
+ print_debug("MB\n");
/* The i810 can't handle DIMMs larger than 128MB per
* side. This will fail if the DIMM uses a
@@ -211,9 +211,9 @@ static void spd_set_dram_size(void)
*/
if (dimm_size > 32) {
print_err("DIMM row sizes larger than 128MB not"
- "supported on i810\r\n");
+ "supported on i810\n");
print_err
- ("Attempting to treat as 128MB DIMM\r\n");
+ ("Attempting to treat as 128MB DIMM\n");
dimm_size = 32;
}
@@ -225,19 +225,19 @@ static void spd_set_dram_size(void)
print_debug("After translation, dimm_size is 0x");
print_debug_hex8(dimm_size);
- print_debug("\r\n");
+ print_debug("\n");
/* If the DIMM is dual-sided, the DRP value is +2 */
/* TODO: Figure out asymetrical configurations. */
if ((smbus_read_byte(DIMM_SPD_BASE + i, 127) | 0xf) ==
0xff) {
- print_debug("DIMM is dual-sided\r\n");
+ print_debug("DIMM is dual-sided\n");
dimm_size += 2;
}
} else {
print_debug("No DIMM found in slot ");
print_debug_hex8(i);
- print_debug("\r\n");
+ print_debug("\n");
/* If there's no DIMM in the slot, set value to 0. */
dimm_size = 0x00;
@@ -249,7 +249,7 @@ static void spd_set_dram_size(void)
print_debug("DRP calculated to 0x");
print_debug_hex8(drp);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config8(PCI_DEV(0, 0, 0), DRP, drp);
}
@@ -354,7 +354,7 @@ static void set_dram_buffer_strength(void)
print_debug("BUFF_SC calculated to 0x");
print_debug_hex16(buff_sc);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config16(PCI_DEV(0, 0, 0), BUFF_SC, buff_sc);
}
@@ -411,32 +411,32 @@ static void sdram_enable(void)
int i;
/* 1. Apply NOP. */
- PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
+ PRINT_DEBUG("RAM Enable 1: Apply NOP\n");
do_ram_command(RAM_COMMAND_NOP);
udelay(200);
/* 2. Precharge all. Wait tRP. */
- PRINT_DEBUG("RAM Enable 2: Precharge all\r\n");
+ PRINT_DEBUG("RAM Enable 2: Precharge all\n");
do_ram_command(RAM_COMMAND_PRECHARGE);
udelay(1);
/* 3. Perform 8 refresh cycles. Wait tRC each time. */
- PRINT_DEBUG("RAM Enable 3: CBR\r\n");
+ PRINT_DEBUG("RAM Enable 3: CBR\n");
for (i = 0; i < 8; i++) {
do_ram_command(RAM_COMMAND_CBR);
udelay(1);
}
/* 4. Mode register set. Wait two memory cycles. */
- PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
+ PRINT_DEBUG("RAM Enable 4: Mode register set\n");
do_ram_command(RAM_COMMAND_MRS);
udelay(2);
/* 5. Normal operation (enables refresh at 15.6usec). */
- PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
+ PRINT_DEBUG("RAM Enable 5: Normal operation\n");
do_ram_command(RAM_COMMAND_NORMAL);
udelay(1);
- PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
+ PRINT_DEBUG("Northbridge following SDRAM init:\n");
DUMPNORTH();
}
diff --git a/src/northbridge/intel/i82830/raminit.c b/src/northbridge/intel/i82830/raminit.c
index f97eaa893d..c9cbdbb8ec 100644
--- a/src/northbridge/intel/i82830/raminit.c
+++ b/src/northbridge/intel/i82830/raminit.c
@@ -79,7 +79,7 @@ static void do_ram_command(u32 command)
pci_write_config32(NORTHBRIDGE, DRC, reg32);
PRINT_DEBUG("RAM command 0x");
PRINT_DEBUG_HEX32(reg32);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
}
static void ram_read32(u8 dimm_start, u32 offset)
@@ -89,24 +89,24 @@ static void ram_read32(u8 dimm_start, u32 offset)
PRINT_DEBUG_HEX32(dimm_start * 32 * 1024 * 1024);
PRINT_DEBUG(" => 0x");
PRINT_DEBUG_HEX32(read32(dimm_start * 32 * 1024 * 1024));
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
PRINT_DEBUG(" Writing RAM at 0x");
PRINT_DEBUG_HEX32(dimm_start * 32 * 1024 * 1024);
PRINT_DEBUG(" <= 0x");
PRINT_DEBUG_HEX32(offset);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
write32(dimm_start * 32 * 1024 * 1024, offset);
PRINT_DEBUG(" Reading RAM at 0x");
PRINT_DEBUG_HEX32(dimm_start * 32 * 1024 * 1024);
PRINT_DEBUG(" => 0x");
PRINT_DEBUG_HEX32(read32(dimm_start * 32 * 1024 * 1024));
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
} else {
PRINT_DEBUG(" Sending RAM command to 0x");
PRINT_DEBUG_HEX32((dimm_start * 32 * 1024 * 1024) + offset);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
read32((dimm_start * 32 * 1024 * 1024) + offset);
}
}
@@ -141,7 +141,7 @@ static void initialize_dimm_rows(void)
if (dimm_end > dimm_start) {
print_debug("Initializing SDRAM Row ");
print_debug_hex8(row);
- print_debug("\r\n");
+ print_debug("\n");
/* NOP command */
PRINT_DEBUG(" NOP ");
@@ -177,7 +177,7 @@ static void initialize_dimm_rows(void)
udelay(1);
/* Perform a dummy memory read/write cycle */
- PRINT_DEBUG(" Performing dummy read/write\r\n");
+ PRINT_DEBUG(" Performing dummy read/write\n");
ram_read32(dimm_start, 0x55aa55aa);
udelay(1);
}
@@ -256,29 +256,29 @@ static void set_dram_row_boundaries(void)
if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) {
print_debug("Found DIMM in slot ");
print_debug_hex8(i);
- print_debug("\r\n");
+ print_debug("\n");
sz = spd_get_dimm_size(device);
/* WISHLIST: would be nice to display it as decimal? */
print_debug("DIMM is 0x");
print_debug_hex16(sz.side1);
- print_debug(" on side 1\r\n");
+ print_debug(" on side 1\n");
print_debug("DIMM is 0x");
print_debug_hex16(sz.side2);
- print_debug(" on side 2\r\n");
+ print_debug(" on side 2\n");
/* - Memory compatibility checks - */
/* Test for PC133 (i82830 only supports PC133) */
/* PC133 SPD9 - cycle time is always 75 */
if (spd_read_byte(device, SPD_MIN_CYCLE_TIME_AT_CAS_MAX) != 0x75) {
- print_err("SPD9 DIMM Is Not PC133 Compatable\r\n");
- die("HALT\r\n");
+ print_err("SPD9 DIMM Is Not PC133 Compatable\n");
+ die("HALT\n");
}
/* PC133 SPD10 - access time is always 54 */
if (spd_read_byte(device, SPD_ACCESS_TIME_FROM_CLOCK) != 0x54) {
- print_err("SPD10 DIMM Is Not PC133 Compatable\r\n");
- die("HALT\r\n");
+ print_err("SPD10 DIMM Is Not PC133 Compatable\n");
+ die("HALT\n");
}
/* The i82830 only supports a symmetrical dual-sided dimms
@@ -286,23 +286,23 @@ static void set_dram_row_boundaries(void)
* side or larger than 256MB per side.
*/
if ((sz.side2 != 0) && (sz.side1 != sz.side2)) {
- print_err("This northbridge only supports\r\n");
- print_err("symmetrical dual-sided DIMMs\r\n");
- print_err("booting as a single-sided DIMM\r\n");
+ print_err("This northbridge only supports\n");
+ print_err("symmetrical dual-sided DIMMs\n");
+ print_err("booting as a single-sided DIMM\n");
sz.side2 = 0;
}
if ((sz.side1 < 32)) {
- print_err("DIMMs smaller than 32MB per side\r\n");
- print_err("are not supported on this northbridge\r\n");
- die("HALT\r\n");
+ print_err("DIMMs smaller than 32MB per side\n");
+ print_err("are not supported on this northbridge\n");
+ die("HALT\n");
}
if ((sz.side1 > 256)) {
print_err
- ("DIMMs larger than 256MB per side\r\n");
+ ("DIMMs larger than 256MB per side\n");
print_err
- ("are not supported on this northbridge\r\n");
- die("HALT\r\n");
+ ("are not supported on this northbridge\n");
+ die("HALT\n");
}
/* - End Memory compatibility checks - */
@@ -316,7 +316,7 @@ static void set_dram_row_boundaries(void)
} else {
PRINT_DEBUG("No DIMM found in slot ");
PRINT_DEBUG_HEX8(i);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
/* If there's no DIMM in the slot, set value to 0. */
drb1 = 0;
@@ -330,12 +330,12 @@ static void set_dram_row_boundaries(void)
PRINT_DEBUG_HEX8(DRB);
PRINT_DEBUG(" has been set to 0x");
PRINT_DEBUG_HEX8(drb1);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
PRINT_DEBUG("DRB1 0x");
PRINT_DEBUG_HEX8(DRB + 1);
PRINT_DEBUG(" has been set to 0x");
PRINT_DEBUG_HEX8(drb1 + drb2);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
} else if (i == 1) {
value = pci_read_config8(NORTHBRIDGE, DRB + 1);
pci_write_config8(NORTHBRIDGE, DRB + 2, value + drb1);
@@ -344,12 +344,12 @@ static void set_dram_row_boundaries(void)
PRINT_DEBUG_HEX8(DRB + 2);
PRINT_DEBUG(" has been set to 0x");
PRINT_DEBUG_HEX8(value + drb1);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
PRINT_DEBUG("DRB3 0x");
PRINT_DEBUG_HEX8(DRB + 3);
PRINT_DEBUG(" has been set to 0x");
PRINT_DEBUG_HEX8(value + drb1 + drb2);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
/* We need to set the highest DRB value to 0x64 and 0x65.
* These are supposed to be "Reserved" but memory will
@@ -374,7 +374,7 @@ static void set_dram_row_attributes(void)
if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) {
print_debug("Found DIMM in slot ");
print_debug_hex8(i);
- print_debug(", setting DRA...\r\n");
+ print_debug(", setting DRA...\n");
dra = 0x00;
@@ -403,8 +403,8 @@ static void set_dram_row_attributes(void)
} else if (dra == 16) {
dra = 0xF3; /* 16KB */
} else {
- print_err("Page size not supported\r\n");
- die("HALT\r\n");
+ print_err("Page size not supported\n");
+ die("HALT\n");
}
} else if (value == 2) {
if (dra == 2) {
@@ -416,18 +416,18 @@ static void set_dram_row_attributes(void)
} else if (dra == 16) {
dra = 0x33; /* 16KB */
} else {
- print_err("Page size not supported\r\n");
- die("HALT\r\n");
+ print_err("Page size not supported\n");
+ die("HALT\n");
}
} else {
- print_err("# of banks of DIMM not supported\r\n");
- die("HALT\r\n");
+ print_err("# of banks of DIMM not supported\n");
+ die("HALT\n");
}
} else {
PRINT_DEBUG("No DIMM found in slot ");
PRINT_DEBUG_HEX8(i);
- PRINT_DEBUG(", setting DRA to 0xFF\r\n");
+ PRINT_DEBUG(", setting DRA to 0xFF\n");
/* If there's no DIMM in the slot, set dra value to 0xFF. */
dra = 0xFF;
@@ -439,7 +439,7 @@ static void set_dram_row_attributes(void)
PRINT_DEBUG_HEX8(DRA + i);
PRINT_DEBUG(" has been set to 0x");
PRINT_DEBUG_HEX8(dra);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
}
}
@@ -468,7 +468,7 @@ Public interface.
static void sdram_set_registers(void)
{
- PRINT_DEBUG("Setting initial sdram registers....\r\n");
+ PRINT_DEBUG("Setting initial sdram registers....\n");
/* Calculate the value for DRT DRAM Timing Register */
set_dram_timing();
@@ -482,7 +482,7 @@ static void sdram_set_registers(void)
/* Setup DRAM Row Attribute Registers */
set_dram_row_attributes();
- PRINT_DEBUG("Initial sdram registers have been set.\r\n");
+ PRINT_DEBUG("Initial sdram registers have been set.\n");
}
static void northbridge_set_registers(void)
@@ -490,7 +490,7 @@ static void northbridge_set_registers(void)
u16 value;
int igd_memory = 0;
- PRINT_DEBUG("Setting initial nothbridge registers....\r\n");
+ PRINT_DEBUG("Setting initial nothbridge registers....\n");
/* Set the value for Fixed DRAM Hole Control Register */
pci_write_config8(NORTHBRIDGE, FDHC, 0x00);
@@ -536,7 +536,7 @@ static void northbridge_set_registers(void)
value |= 1; // 64MB aperture
pci_write_config16(NORTHBRIDGE, GCC1, value);
- PRINT_DEBUG("Initial northbridge registers have been set.\r\n");
+ PRINT_DEBUG("Initial northbridge registers have been set.\n");
}
static void sdram_initialize(void)
@@ -554,13 +554,13 @@ static void sdram_initialize(void)
initialize_dimm_rows();
/* Enable Refresh */
- PRINT_DEBUG("Enabling Refresh\r\n");
+ PRINT_DEBUG("Enabling Refresh\n");
reg32 = pci_read_config32(NORTHBRIDGE, DRC);
reg32 |= (RAM_COMMAND_REFRESH << 8);
pci_write_config32(NORTHBRIDGE, DRC, reg32);
/* Set initialization complete */
- PRINT_DEBUG("Setting initialization complete\r\n");
+ PRINT_DEBUG("Setting initialization complete\n");
reg32 = pci_read_config32(NORTHBRIDGE, DRC);
reg32 |= (RAM_COMMAND_IC << 29);
pci_write_config32(NORTHBRIDGE, DRC, reg32);
@@ -568,6 +568,6 @@ static void sdram_initialize(void)
/* Setup Initial Northbridge Registers */
northbridge_set_registers();
- PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
+ PRINT_DEBUG("Northbridge following SDRAM init:\n");
DUMPNORTH();
}
diff --git a/src/northbridge/intel/i855/debug.c b/src/northbridge/intel/i855/debug.c
index 4083add6f1..40da896589 100644
--- a/src/northbridge/intel/i855/debug.c
+++ b/src/northbridge/intel/i855/debug.c
@@ -60,7 +60,7 @@ static void print_pci_devices(void)
continue;
}
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
}
}
@@ -68,7 +68,7 @@ static void dump_pci_device(unsigned dev)
{
int i;
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i <= 255; i++) {
unsigned char val;
@@ -80,7 +80,7 @@ static void dump_pci_device(unsigned dev)
print_debug_char(' ');
print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) {
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
@@ -105,7 +105,7 @@ static void dump_pci_devices(void)
static void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i < 2; i++) {
unsigned device;
device = ctrl->channel0[i];
@@ -119,20 +119,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
#if 0
device = ctrl->channel1[i];
@@ -146,20 +146,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
#endif
}
@@ -167,7 +167,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
static void dump_smbus_registers(void)
{
int i;
- print_debug("\r\n");
+ print_debug("\n");
for(i = 1; i < 0x80; i++) {
unsigned device;
device = i;
@@ -178,20 +178,20 @@ static void dump_smbus_registers(void)
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
#endif
diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c
index 8e928bd279..136266da2c 100644
--- a/src/northbridge/intel/i855/raminit.c
+++ b/src/northbridge/intel/i855/raminit.c
@@ -31,7 +31,7 @@
static void sdram_set_registers(const struct mem_controller *ctrl)
{
/*
- print_debug("Before configuration:\r\n");
+ print_debug("Before configuration:\n");
dump_pci_devices();
*/
}
@@ -212,7 +212,7 @@ static void ram_command_mrs(const struct mem_controller *ctrl,
adjusted_mode = ((mode & 0x800) << (13 - 11)) | ((mode & 0x3ff) << (12 - 9));
print_debug("Setting mode: ");
print_debug_hex32(adjusted_mode + addr);
- print_debug("\r\n");
+ print_debug("\n");
read32(adjusted_mode + addr);
}
@@ -229,39 +229,39 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
{
int i;
uint32_t rank1 = (1 << 30) / 2;
- print_debug("Ram enable 1\r\n");
+ print_debug("Ram enable 1\n");
delay();
delay();
- print_debug("Ram enable 2\r\n");
+ print_debug("Ram enable 2\n");
ram_command(ctrl, 1, 0);
ram_command(ctrl, 1, rank1);
delay();
delay();
- print_debug("Ram enable 3\r\n");
+ print_debug("Ram enable 3\n");
ram_command(ctrl, 2, 0);
ram_command(ctrl, 2, rank1);
delay();
delay();
- print_debug("Ram enable 4\r\n");
+ print_debug("Ram enable 4\n");
ram_command_mrs(ctrl, 4, SDRAM_EXTMODE_DLL_ENABLE, 0);
ram_command_mrs(ctrl, 4, SDRAM_EXTMODE_DLL_ENABLE, rank1);
delay();
delay();
- print_debug("Ram enable 5\r\n");
+ print_debug("Ram enable 5\n");
ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_DLL_RESET, 0);
ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_DLL_RESET, rank1);
- print_debug("Ram enable 6\r\n");
+ print_debug("Ram enable 6\n");
ram_command(ctrl, 2, 0);
ram_command(ctrl, 2, rank1);
delay();
delay();
- print_debug("Ram enable 7\r\n");
+ print_debug("Ram enable 7\n");
for(i = 0; i < 8; i++) {
ram_command(ctrl, 6, 0);
ram_command(ctrl, 6, rank1);
@@ -269,28 +269,28 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
delay();
}
- print_debug("Ram enable 8\r\n");
+ print_debug("Ram enable 8\n");
ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_NORMAL, 0);
ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_NORMAL, rank1);
- print_debug("Ram enable 9\r\n");
+ print_debug("Ram enable 9\n");
ram_command(ctrl, 7, 0);
ram_command(ctrl, 7, rank1);
delay();
delay();
- print_debug("Ram enable 9\r\n");
+ print_debug("Ram enable 9\n");
set_initialize_complete(ctrl);
delay();
delay();
delay();
- print_debug("After configuration:\r\n");
+ print_debug("After configuration:\n");
/* dump_pci_devices(); */
/*
- print_debug("\n\n***** RAM TEST *****\r\n");
+ print_debug("\n\n***** RAM TEST *****\n");
ram_check(0, 0xa0000);
ram_check(0x100000, 0x40000000);
*/
diff --git a/src/northbridge/via/cn400/raminit.c b/src/northbridge/via/cn400/raminit.c
index 577d53b05b..7f7c997077 100644
--- a/src/northbridge/via/cn400/raminit.c
+++ b/src/northbridge/via/cn400/raminit.c
@@ -151,7 +151,7 @@ static void ddr_ram_setup(void)
unsigned long bank_address;
- print_debug("CN400 RAM init starting\r\n");
+ print_debug("CN400 RAM init starting\n");
pci_write_config8(ctrl.d0f7, 0x75, 0x08);
@@ -176,7 +176,7 @@ static void ddr_ram_setup(void)
*/
c = 0;
b = smbus_read_byte(0x50, SPD_NUM_BANKS_PER_SDRAM);
- //print_val("Detecting Memory\r\nNumber of Banks ",b);
+ //print_val("Detecting Memory\nNumber of Banks ",b);
// Only supporting 4 bank chips just now
if( b == 4 ){
@@ -186,7 +186,7 @@ static void ddr_ram_setup(void)
c = 0x01;
bank = 0x40;
b = smbus_read_byte(0x50, SPD_NUM_ROWS);
- //print_val("\r\nNumber of Rows ", b);
+ //print_val("\nNumber of Rows ", b);
if( b >= 0x0d ){ // 256/512Mb
@@ -199,7 +199,7 @@ static void ddr_ram_setup(void)
Read SPD byte 13, Primary DRAM width.
*/
b = smbus_read_byte(0x50, SPD_PRIMARY_SDRAM_WIDTH);
- //print_val("\r\nPrimary DRAM width", b);
+ //print_val("\nPrimary DRAM width", b);
if( b != 4 ) // not 64/128Mb (x4)
c = 0x81; // 256Mb
}
@@ -208,12 +208,12 @@ static void ddr_ram_setup(void)
Read SPD byte 4, Number of column addresses.
*/
b = smbus_read_byte(0x50, SPD_NUM_COLUMNS);
- //print_val("\r\nNo Columns ",b);
+ //print_val("\nNo Columns ",b);
if( b == 10 || b == 11 || b == 12) c |= 0x60; // 10/11 bit col addr
if( b == 9 ) c |= 0x40; // 9 bit col addr
if( b == 8 ) c |= 0x20; // 8 bit col addr
- //print_val("\r\nMA type ", c);
+ //print_val("\nMA type ", c);
pci_write_config8(ctrl.d0f3, 0x50, c);
}
@@ -223,7 +223,7 @@ static void ddr_ram_setup(void)
/* else
{
- die("DRAM module size is not supported by CN400\r\n");
+ die("DRAM module size is not supported by CN400\n");
}
*/
@@ -281,7 +281,7 @@ static void ddr_ram_setup(void)
// SPD byte 5 # of physical banks
b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS);
- //print_val("\r\nNo Physical Banks ",b);
+ //print_val("\nNo Physical Banks ",b);
if( b == 2)
{
c <<=1;
@@ -289,7 +289,7 @@ static void ddr_ram_setup(void)
}
/* else
{
- die("Only a single DIMM is supported by EPIA-N(L)\r\n");
+ die("Only a single DIMM is supported by EPIA-N(L)\n");
}
*/
// set banks 1,2,3...
@@ -309,7 +309,7 @@ static void ddr_ram_setup(void)
/* Read SPD byte 18 CAS Latency */
b = smbus_read_byte(0x50, SPD_ACCEPTABLE_CAS_LATENCIES);
-/* print_debug("\r\nCAS Supported ");
+/* print_debug("\nCAS Supported ");
if(b & 0x04)
print_debug("2 ");
if(b & 0x08)
@@ -318,11 +318,11 @@ static void ddr_ram_setup(void)
print_debug("3");
c = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
- print_val("\r\nCycle time at CL X (nS)", c);
+ print_val("\nCycle time at CL X (nS)", c);
c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND);
- print_val("\r\nCycle time at CL X-0.5 (nS)", c);
+ print_val("\nCycle time at CL X-0.5 (nS)", c);
c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD);
- print_val("\r\nCycle time at CL X-1 (nS)", c);
+ print_val("\nCycle time at CL X-1 (nS)", c);
*/
/* Scaling of Cycle Time SPD data */
/* 7 4 3 0 */
@@ -330,27 +330,27 @@ static void ddr_ram_setup(void)
bank = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
if( b & 0x10 ){ // DDR offering optional CAS 3
- //print_debug("\r\nStarting at CAS 3");
+ //print_debug("\nStarting at CAS 3");
c = 0x30;
/* see if we can better it */
if( b & 0x08 ){ // DDR mandatory CAS 2.5
if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND) <= bank ){ // we can manage max MHz at CAS 2.5
- //print_debug("\r\nWe can do CAS 2.5");
+ //print_debug("\nWe can do CAS 2.5");
c = 0x20;
}
}
if( b & 0x04 ){ // DDR mandatory CAS 2
if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max Mhz at CAS 2
- //print_debug("\r\nWe can do CAS 2");
+ //print_debug("\nWe can do CAS 2");
c = 0x10;
}
}
}else{ // no optional CAS values just 2 & 2.5
- //print_debug("\r\nStarting at CAS 2.5");
+ //print_debug("\nStarting at CAS 2.5");
c = 0x20; // assume CAS 2.5
if( b & 0x04){ // Should always happen
if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max Mhz at CAS 2
- //print_debug("\r\nWe can do CAS 2");
+ //print_debug("\nWe can do CAS 2");
c = 0x10;
}
}
@@ -386,7 +386,7 @@ static void ddr_ram_setup(void)
b = smbus_read_byte(0x50, SPD_MIN_ROW_PRECHARGE_TIME);
- //print_val("\r\ntRP ",b);
+ //print_val("\ntRP ",b);
if ( b >= (5 * bank)) {
c |= 0x03; // set tRP = 5T
}
@@ -404,7 +404,7 @@ static void ddr_ram_setup(void)
*/
b = smbus_read_byte(0x50, SPD_MIN_RAS_TO_CAS_DELAY);
- //print_val("\r\ntRCD ",b);
+ //print_val("\ntRCD ",b);
if ( b >= (5 * bank)) c |= 0x0C; // set tRCD = 5T
else if ( b >= (4 * bank)) c |= 0x08; // set tRCD = 4T
@@ -421,8 +421,8 @@ static void ddr_ram_setup(void)
bank = bank >> 2;
b = smbus_read_byte(0x50, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
- //print_val("\r\ntRAS ",b);
- //print_val("\r\nBank ", bank);
+ //print_val("\ntRAS ",b);
+ //print_val("\nBank ", bank);
if ( b >= (9 * bank)) c |= 0xC0; // set tRAS = 9T
else if ( b >= (8 * bank)) c |= 0x80; // set tRAS = 8T
else if ( b >= (7 * bank)) c |= 0x40; // set tRAS = 7T
@@ -537,7 +537,7 @@ static void ddr_ram_setup(void)
c &= 0x08;
if ( c == 0x08 )
{
- print_debug("Setting Burst Length 8\r\n");
+ print_debug("Setting Burst Length 8\n");
/*
CPU Frequency Device 0 Function 2 Offset 54
@@ -723,7 +723,7 @@ static void ddr_ram_setup(void)
break;
}
- print_val("\r\nLow Bond ",i);
+ print_val("\nLow Bond ",i);
if( i < 0xff ){
c = i++;
for( ; i <0xff ; i++){
@@ -767,7 +767,7 @@ static void ddr_ram_setup(void)
print_val(" High Bond ",i);
c = ((i - c)<<1)/3 + c;
print_val(" Setting DQS delay",c);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config8(ctrl.d0f3,0x70,c);
}else{
pci_write_config8(ctrl.d0f3,0x70,0x67);
@@ -822,5 +822,5 @@ static void ddr_ram_setup(void)
/* VGA device. */
pci_write_config16(ctrl.d0f3, 0xa0, (1 << 15));
pci_write_config16(ctrl.d0f3, 0xa4, 0x0010);
- print_debug("CN400 raminit.c done\r\n");
+ print_debug("CN400 raminit.c done\n");
}
diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c
index bddb4448fe..72fb0c5a26 100644
--- a/src/northbridge/via/cn700/raminit.c
+++ b/src/northbridge/via/cn700/raminit.c
@@ -183,7 +183,7 @@ static void sdram_set_size(const struct mem_controller *ctrl)
}
if (result == 0xff)
- die("DRAM module size too big, not supported by CN700\r\n");
+ die("DRAM module size too big, not supported by CN700\n");
pci_write_config8(ctrl->d0f3, 0x40, result);
pci_write_config8(ctrl->d0f3, 0x48, 0x00);
@@ -389,30 +389,30 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
u8 i;
/* 1. Apply NOP. */
- PRINT_DEBUG_MEM("RAM Enable 1: Apply NOP\r\n");
+ PRINT_DEBUG_MEM("RAM Enable 1: Apply NOP\n");
do_ram_command(dev, RAM_COMMAND_NOP);
udelay(100);
read32(rank_address + 0x10);
/* 2. Precharge all. */
udelay(400);
- PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\r\n");
+ PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n");
do_ram_command(dev, RAM_COMMAND_PRECHARGE);
read32(rank_address + 0x10);
/* 3. Mode register set. */
- PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n");
+ PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n");
do_ram_command(dev, RAM_COMMAND_MRS);
read32(rank_address + 0x120000); /* EMRS DLL Enable */
read32(rank_address + 0x800); /* MRS DLL Reset */
/* 4. Precharge all again. */
- PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\r\n");
+ PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n");
do_ram_command(dev, RAM_COMMAND_PRECHARGE);
read32(rank_address + 0x0);
/* 5. Perform 8 refresh cycles. Wait tRC each time. */
- PRINT_DEBUG_MEM("RAM Enable 3: CBR\r\n");
+ PRINT_DEBUG_MEM("RAM Enable 3: CBR\n");
do_ram_command(dev, RAM_COMMAND_CBR);
for (i = 0; i < 8; i++) {
read32(rank_address + 0x20);
@@ -420,7 +420,7 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
}
/* 6. Mode register set. */
- PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n");
+ PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n");
/* Safe value for now, BL=8, WR=5, CAS=4 */
/*
* (E)MRS values are from the BPG. No direct explanation is given, but
@@ -433,7 +433,7 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
read32(rank_address + 0x120020); /* EMRS OCD Calibration Mode Exit */
/* 8. Normal operation */
- PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\r\n");
+ PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\n");
do_ram_command(dev, RAM_COMMAND_NORMAL);
read32(rank_address + 0x30);
}
diff --git a/src/northbridge/via/cx700/cx700_early_smbus.c b/src/northbridge/via/cx700/cx700_early_smbus.c
index ccee3b4633..361b5e9bca 100644
--- a/src/northbridge/via/cx700/cx700_early_smbus.c
+++ b/src/northbridge/via/cx700/cx700_early_smbus.c
@@ -66,25 +66,25 @@ static void smbus_print_error(unsigned char host_status_register, int loops)
print_err("SMBus Error: ");
print_err_hex8(host_status_register);
- print_err("\r\n");
+ print_err("\n");
if (loops >= SMBUS_TIMEOUT) {
- print_err("SMBus Timout\r\n");
+ print_err("SMBus Timout\n");
}
if (host_status_register & (1 << 4)) {
- print_err("Interrup/SMI# was Failed Bus Transaction\r\n");
+ print_err("Interrup/SMI# was Failed Bus Transaction\n");
}
if (host_status_register & (1 << 3)) {
- print_err("Bus Error\r\n");
+ print_err("Bus Error\n");
}
if (host_status_register & (1 << 2)) {
- print_err("Device Error\r\n");
+ print_err("Device Error\n");
}
if (host_status_register & (1 << 1)) {
/* This isn't a real error... */
- print_debug("Interrupt/SMI# was Successful Completion\r\n");
+ print_debug("Interrupt/SMI# was Successful Completion\n");
}
if (host_status_register & (1 << 0)) {
- print_err("Host Busy\r\n");
+ print_err("Host Busy\n");
}
}
@@ -240,7 +240,7 @@ static void dump_spd_data(const struct mem_controller *ctrl)
for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) {
print_debug("SPD Data for DIMM ");
print_debug_hex8(dimm);
- print_debug("\r\n");
+ print_debug("\n");
val = get_spd_data(ctrl, dimm, 0);
if (val == 0xff) {
@@ -248,7 +248,7 @@ static void dump_spd_data(const struct mem_controller *ctrl)
} else if (val == 0x80) {
regs = 128;
} else {
- print_debug("No DIMM present\r\n");
+ print_debug("No DIMM present\n");
regs = 0;
}
for (offset = 0; offset < regs; offset++) {
@@ -256,7 +256,7 @@ static void dump_spd_data(const struct mem_controller *ctrl)
print_debug_hex8(offset);
print_debug(" = 0x");
print_debug_hex8(get_spd_data(ctrl, dimm, offset));
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
diff --git a/src/northbridge/via/vt8601/raminit.c b/src/northbridge/via/vt8601/raminit.c
index 65c8088e68..2042d62d27 100644
--- a/src/northbridge/via/vt8601/raminit.c
+++ b/src/northbridge/via/vt8601/raminit.c
@@ -79,7 +79,7 @@ void dumpnorth(device_t north)
print_debug_hex8(pci_read_config8(north, r + c));
print_debug(" ");
}
- print_debug("\r\n");
+ print_debug("\n");
if (r >= 240)
break;
}
@@ -90,13 +90,13 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
device_t north = (device_t) PCI_DEV(0, 0, 0);
uint8_t c, r;
- print_err("vt8601 init starting\r\n");
+ print_err("vt8601 init starting\n");
print_debug_hex32(north);
print_debug(" is the north\n");
print_debug_hex16(pci_read_config16(north, 0));
print_debug(" ");
print_debug_hex16(pci_read_config16(north, 2));
- print_debug("\r\n");
+ print_debug("\n");
/* All we are doing now is setting initial known-good values that will
* be revised later as we read SPD
@@ -186,7 +186,7 @@ static unsigned long spd_module_size(unsigned char slot)
print_info("Slot ");
print_info_hex8(slot);
if (smbus_read_byte(module, 2) != 4) {
- print_info(" is empty\r\n");
+ print_info(" is empty\n");
return 0;
}
print_info(" is SDRAM ");
@@ -211,7 +211,7 @@ static unsigned long spd_module_size(unsigned char slot)
print_info("x2");
value = (value << 16) | value;
}
- print_info("\r\n");
+ print_info("\n");
return value;
}
@@ -288,19 +288,19 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* set NOP */
pci_write_config8(north, 0x6C, 0x01);
- print_debug("NOP\r\n");
+ print_debug("NOP\n");
/* wait 200us */
// You need to do the memory reference. That causes the nop cycle.
dimms_read(0);
udelay(400);
- print_debug("PRECHARGE\r\n");
+ print_debug("PRECHARGE\n");
/* set precharge */
pci_write_config8(north, 0x6C, 0x02);
- print_debug("DUMMY READS\r\n");
+ print_debug("DUMMY READS\n");
/* dummy reads */
dimms_read(0);
udelay(200);
- print_debug("CBR\r\n");
+ print_debug("CBR\n");
/* set CBR */
pci_write_config8(north, 0x6C, 0x04);
@@ -321,7 +321,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
udelay(200);
dimms_read(0);
udelay(200);
- print_debug("MRS\r\n");
+ print_debug("MRS\n");
/* set MRS */
pci_write_config8(north, 0x6c, 0x03);
#if DIMM_CL2
@@ -330,21 +330,21 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
dimms_read(0x1d0);
#endif
udelay(200);
- print_debug("NORMAL\r\n");
+ print_debug("NORMAL\n");
/* set to normal mode */
pci_write_config8(north, 0x6C, 0x08);
dimms_write(0x55aa55aa);
dimms_read(0);
udelay(200);
- print_debug("set ref. rate\r\n");
+ print_debug("set ref. rate\n");
// Set the refresh rate.
#if DIMM_PC133
pci_write_config8(north, 0x6A, 0x86);
#else
pci_write_config8(north, 0x6A, 0x65);
#endif
- print_debug("enable multi-page open\r\n");
+ print_debug("enable multi-page open\n");
// enable multi-page open
pci_write_config8(north, 0x6B, 0x0d);
@@ -381,8 +381,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
else /* 256MB or more per side */
ma = 0xe;
print_debug_hex16(ma);
- print_debug(" is the MA type\r\n");
+ print_debug(" is the MA type\n");
set_ma_mapping(north, slot, ma);
}
- print_err("vt8601 done\r\n");
+ print_err("vt8601 done\n");
}
diff --git a/src/northbridge/via/vt8623/raminit.c b/src/northbridge/via/vt8623/raminit.c
index ffae808936..40338dae7e 100644
--- a/src/northbridge/via/vt8623/raminit.c
+++ b/src/northbridge/via/vt8623/raminit.c
@@ -56,7 +56,7 @@ dumpnorth(device_t north)
print_debug_hex8(pci_read_config8(north, r+c));
print_debug(" ");
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
void print_val(char *str, int val)
@@ -72,7 +72,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
uint16_t i,j;
unsigned long bank_address;
- print_debug("vt8623 init starting\r\n");
+ print_debug("vt8623 init starting\n");
north = pci_locate_device(PCI_ID(0x1106, 0x3123), 0);
north = 0;
@@ -102,7 +102,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
*/
c = 0;
b = smbus_read_byte(0xa0,17);
- print_val("Detecting Memory\r\nNumber of Banks ",b);
+ print_val("Detecting Memory\nNumber of Banks ",b);
if( b != 2 ){ // not 16 Mb type
@@ -110,14 +110,14 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
Read SPD byte 3, Number of row addresses.
*/
b = smbus_read_byte(0xa0,3);
- print_val("\r\nNumber of Rows ",b);
+ print_val("\nNumber of Rows ",b);
if( b >= 0x0d ){ // not 64/128Mb (rows <=12)
/*
Read SPD byte 13, Primary DRAM width.
*/
b = smbus_read_byte(0xa0,13);
- print_val("\r\nPriamry DRAM width",b);
+ print_val("\nPriamry DRAM width",b);
if( b != 4 ) // mot 64/128Mb (x4)
c = 0x80; // 256Mb
}
@@ -128,13 +128,13 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
Read SPD byte 4, Number of column addresses.
*/
b = smbus_read_byte(0xa0,4);
- print_val("\r\nNo Columns ",b);
+ print_val("\nNo Columns ",b);
if( b == 10 || b == 11 ) c |= 0x60; // 10/11 bit col addr
if( b == 9 ) c |= 0x40; // 9 bit col addr
if( b == 8 ) c |= 0x20; // 8 bit col addr
}
- print_val("\r\nMA type ",c);
+ print_val("\nMA type ",c);
pci_write_config8(north,0x58,c);
/*
@@ -161,18 +161,18 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
else c = 0x01; // Error, use default
- print_val("\r\nBank 0 (*16 Mb) ",c);
+ print_val("\nBank 0 (*16 Mb) ",c);
// set bank zero size
pci_write_config8(north,0x5a,c);
// SPD byte 5 # of physical banks
b = smbus_read_byte(0xa0,5);
- print_val("\r\nNo Physical Banks ",b);
+ print_val("\nNo Physical Banks ",b);
if( b == 2)
c <<=1;
- print_val("\r\nTotal Memory (*16 Mb) ",c);
+ print_val("\nTotal Memory (*16 Mb) ",c);
// set banks 1,2,3
pci_write_config8(north,0x5b,c);
pci_write_config8(north,0x5c,c);
@@ -181,40 +181,40 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
/* Read SPD byte 18 CAS Latency */
b = smbus_read_byte(0xa0,18);
- print_debug("\r\nCAS Supported ");
+ print_debug("\nCAS Supported ");
if(b & 0x04)
print_debug("2 ");
if(b & 0x08)
print_debug("2.5 ");
if(b & 0x10)
print_debug("3");
- print_val("\r\nCycle time at CL X (nS)",smbus_read_byte(0xa0,9));
- print_val("\r\nCycle time at CL X-0.5 (nS)",smbus_read_byte(0xa0,23));
- print_val("\r\nCycle time at CL X-1 (nS)",smbus_read_byte(0xa0,25));
+ print_val("\nCycle time at CL X (nS)",smbus_read_byte(0xa0,9));
+ print_val("\nCycle time at CL X-0.5 (nS)",smbus_read_byte(0xa0,23));
+ print_val("\nCycle time at CL X-1 (nS)",smbus_read_byte(0xa0,25));
if( b & 0x10 ){ // DDR offering optional CAS 3
- print_debug("\r\nStarting at CAS 3");
+ print_debug("\nStarting at CAS 3");
c = 0x30;
/* see if we can better it */
if( b & 0x08 ){ // DDR mandatory CAS 2.5
if( smbus_read_byte(0xa0,23) <= 0x75 ){ // we can manage 133Mhz at CAS 2.5
- print_debug("\r\nWe can do CAS 2.5");
+ print_debug("\nWe can do CAS 2.5");
c = 0x20;
}
}
if( b & 0x04 ){ // DDR mandatory CAS 2
if( smbus_read_byte(0xa0,25) <= 0x75 ){ // we can manage 133Mhz at CAS 2
- print_debug("\r\nWe can do CAS 2");
+ print_debug("\nWe can do CAS 2");
c = 0x10;
}
}
}else{ // no optional CAS values just 2 & 2.5
- print_debug("\r\nStarting at CAS 2.5");
+ print_debug("\nStarting at CAS 2.5");
c = 0x20; // assume CAS 2.5
if( b & 0x04){ // Should always happen
if( smbus_read_byte(0xa0,23) <= 0x75){ // we can manage 133Mhz at CAS 2
- print_debug("\r\nWe can do CAS 2");
+ print_debug("\nWe can do CAS 2");
c = 0x10;
}
}
@@ -254,7 +254,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
*/
b = smbus_read_byte(0xa0,27);
- print_val("\r\ntRP ",b);
+ print_val("\ntRP ",b);
if( b > 0x3c ) // set tRP = 3T
c |= 0x80;
@@ -266,7 +266,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
*/
b = smbus_read_byte(0xa0,29);
- print_val("\r\ntRCD ",b);
+ print_val("\ntRCD ",b);
if( b > 0x3c ) // set tRCD = 3T
c |= 0x04;
@@ -278,7 +278,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
*/
b = smbus_read_byte(0xa0,30);
- print_val("\r\ntRAS ",b);
+ print_val("\ntRAS ",b);
if( b > 0x25 ) // set tRAS = 6T
c |= 0x40;
@@ -500,7 +500,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
break;
}
- print_val("\r\nLow Bond ",i);
+ print_val("\nLow Bond ",i);
if( i < 0xff ){
c = i++;
for( ; i <0xff ; i++){
@@ -549,7 +549,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
pci_write_config8(north,0x68,c);
pci_write_config8(north,0x68,0x42);
}else{
- print_debug("Unable to determine low bond - Setting default\r\n");
+ print_debug("Unable to determine low bond - Setting default\n");
pci_write_config8(north,0x68,0x59);
}
@@ -608,10 +608,10 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
pci_write_config8(north,0xac,0x2f);
pci_write_config8(north,0xae,0x04);
- print_debug("vt8623 done\r\n");
+ print_debug("vt8623 done\n");
dumpnorth(north);
- print_debug("AGP\r\n");
+ print_debug("AGP\n");
north = pci_locate_device(PCI_ID(0x1106, 0xb091), 0);
pci_write_config32(north,0x20,0xddf0dc00);
pci_write_config32(north,0x24,0xdbf0d800);
diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c
index 80ee22c22a..22c0fbd40f 100644
--- a/src/northbridge/via/vx800/examples/romstage.c
+++ b/src/northbridge/via/vx800/examples/romstage.c
@@ -52,13 +52,13 @@ int acpi_is_wakeup_early_via_vx800(void)
device_t dev;
u16 tmp, result;
- print_debug("In acpi_is_wakeup_early_via_vx800\r\n");
+ print_debug("In acpi_is_wakeup_early_via_vx800\n");
/* Power management controller */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VX855_LPC), 0);
if (dev == PCI_DEV_INVALID)
- die("Power management controller not found\r\n");
+ die("Power management controller not found\n");
/* Set ACPI base address to I/O VX800_ACPI_IO_BASE. */
pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 0x1);
@@ -70,7 +70,7 @@ int acpi_is_wakeup_early_via_vx800(void)
result = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0;
print_debug(" boot_mode=");
print_debug_hex16(result);
- print_debug("\r\n");
+ print_debug("\n");
return result;
}
@@ -85,7 +85,7 @@ static void enable_mainboard_devices(void)
device_t dev;
uint16_t values;
- print_debug("In enable_mainboard_devices \r\n");
+ print_debug("In enable_mainboard_devices \n");
/*
Enable P2P Bridge Header for External PCI BUS.
@@ -375,14 +375,14 @@ g) Rx73h = 32h
if (bist == 0) {
// CAR need mtrr untill mem is ok, so i disable this early_mtrr_init();
- //print_debug("doing early_mtrr\r\n");
+ //print_debug("doing early_mtrr\n");
//early_mtrr_init();
}
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
- print_debug("Enabling mainboard devices\r\n");
+ print_debug("Enabling mainboard devices\n");
enable_mainboard_devices();
u8 Data;
@@ -392,7 +392,7 @@ g) Rx73h = 32h
Data = pci_read_config8(device, 0xf6);
print_debug("NB chip revision =");
print_debug_hex8(Data);
- print_debug("\r\n");
+ print_debug("\n");
/* make NB ready before draminit */
via_pci_inittable(Data, mNbStage1InitTbl);
@@ -405,7 +405,7 @@ g) Rx73h = 32h
u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
DRAM_SYS_ATTR DramAttr;
- print_debug("This is a S3 wakeup\r\n");
+ print_debug("This is a S3 wakeup\n");
memset(&DramAttr, 0, sizeof(DRAM_SYS_ATTR));
/*Step1 DRAM Detection; DDR1 or DDR2; Get SPD Data; Rank Presence;64 or 128bit; Unbuffered or registered; 1T or 2T */
@@ -429,7 +429,7 @@ g) Rx73h = 32h
DRAMRegFinalValue(&DramAttr); // I just copy this function from draminit to here!
SetUMARam(); // I just copy this function from draminit to here!
- print_debug("Resume from S3, RAM init was ignored\r\n");
+ print_debug("Resume from S3, RAM init was ignored\n");
} else {
ddr2_ram_setup();
ram_check(0, 640 * 1024);
@@ -528,7 +528,7 @@ g) Rx73h = 32h
"rep movsd\n\t"
::"g"(memtop4)
);*/
- print_debug("copy memory to high memory to protect s3 wakeup vector code \r\n"); //this can have function call, because no variable used before this
+ print_debug("copy memory to high memory to protect s3 wakeup vector code \n"); //this can have function call, because no variable used before this
memcpy((unsigned char *) ((*(u32 *) WAKE_MEM_INFO) -
64 * 1024 - 0x100000),
(unsigned char *) 0, 0xa0000);
@@ -572,11 +572,11 @@ So, I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c hav
__asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp)
);
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp);
+ printk(BIOS_DEBUG, "v_esp=%08x\n", v_esp);
#else
print_debug("v_esp=");
print_debug_hex32(v_esp);
- print_debug("\r\n");
+ print_debug("\n");
#endif
}
@@ -588,11 +588,11 @@ So, I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c hav
//stack
cpu_reset = 0;
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "cpu_reset = %08x\r\n", cpu_reset);
+ printk(BIOS_DEBUG, "cpu_reset = %08x\n", cpu_reset);
#else
print_debug("cpu_reset = ");
print_debug_hex32(cpu_reset);
- print_debug("\r\n");
+ print_debug("\n");
#endif
if (cpu_reset == 0) {
@@ -635,16 +635,16 @@ So, I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c hav
/* We can not go back any more, we lost old stack data in cache as ram */
if (new_cpu_reset == 0) {
- print_debug("Use Ram as Stack now - done\r\n");
+ print_debug("Use Ram as Stack now - done\n");
} else {
- print_debug("Use Ram as Stack now - \r\n");
+ print_debug("Use Ram as Stack now - \n");
}
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset);
+ printk(BIOS_DEBUG, "new_cpu_reset = %08x\n", new_cpu_reset);
#else
print_debug("new_cpu_reset = ");
print_debug_hex32(new_cpu_reset);
- print_debug("\r\n");
+ print_debug("\n");
#endif
/*copy and execute coreboot_ram */
copy_and_run(new_cpu_reset);
@@ -653,6 +653,6 @@ So, I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c hav
#endif
- print_debug("should not be here -\r\n");
+ print_debug("should not be here -\n");
}
diff --git a/src/northbridge/via/vx800/vga.c b/src/northbridge/via/vx800/vga.c
index 58d70c33c3..ee010a0c8b 100644
--- a/src/northbridge/via/vx800/vga.c
+++ b/src/northbridge/via/vx800/vga.c
@@ -102,7 +102,7 @@ static void vga_init(device_t dev)
}
#else
/* Attempt to manually force the rom to load */
- printk(BIOS_DEBUG, "Forcing rom load\r\n");
+ printk(BIOS_DEBUG, "Forcing rom load\n");
pci_rom_load(dev, 0xfff80000);
run_bios(dev, 0xc0000);
#endif
diff --git a/src/northbridge/via/vx800/vx800_early_smbus.c b/src/northbridge/via/vx800/vx800_early_smbus.c
index 9beb9cf130..93b1461e9a 100644
--- a/src/northbridge/via/vx800/vx800_early_smbus.c
+++ b/src/northbridge/via/vx800/vx800_early_smbus.c
@@ -60,32 +60,32 @@
/* Internal functions */
static void smbus_print_error(unsigned char host_status_register, int loops)
{
-// print_err("some i2c error\r\n");
+// print_err("some i2c error\n");
/* Check if there actually was an error */
if (host_status_register == 0x00 || host_status_register == 0x40 ||
host_status_register == 0x42)
return;
print_err("smbus_error: ");
print_err_hex8(host_status_register);
- print_err("\r\n");
+ print_err("\n");
if (loops >= SMBUS_TIMEOUT) {
- print_err("SMBus Timout\r\n");
+ print_err("SMBus Timout\n");
}
if (host_status_register & (1 << 4)) {
- print_err("Interrup/SMI# was Failed Bus Transaction\r\n");
+ print_err("Interrup/SMI# was Failed Bus Transaction\n");
}
if (host_status_register & (1 << 3)) {
- print_err("Bus Error\r\n");
+ print_err("Bus Error\n");
}
if (host_status_register & (1 << 2)) {
- print_err("Device Error\r\n");
+ print_err("Device Error\n");
}
if (host_status_register & (1 << 1)) {
/* This isn't a real error... */
- print_debug("Interrupt/SMI# was Successful Completion\r\n");
+ print_debug("Interrupt/SMI# was Successful Completion\n");
}
if (host_status_register & (1 << 0)) {
- print_err("Host Busy\r\n");
+ print_err("Host Busy\n");
}
}
@@ -204,7 +204,7 @@ static void enable_smbus(void)
if (dev == PCI_DEV_INVALID) {
/* This won't display text if enable_smbus() is before serial init */
- die("Power Managment Controller not found\r\n");
+ die("Power Managment Controller not found\n");
}
/* Set clock source */
@@ -253,7 +253,7 @@ void smbus_fixup(const struct mem_controller *ctrl)
ram_slots = ARRAY_SIZE(ctrl->channel0);
if (!ram_slots) {
- print_err("smbus_fixup() thinks there are no RAM slots!\r\n");
+ print_err("smbus_fixup() thinks there are no RAM slots!\n");
return;
}
@@ -279,9 +279,9 @@ void smbus_fixup(const struct mem_controller *ctrl)
}
if (i >= SMBUS_TIMEOUT)
- print_err("SMBus timed out while warming up\r\n");
+ print_err("SMBus timed out while warming up\n");
else
- PRINT_DEBUG("Done\r\n");
+ PRINT_DEBUG("Done\n");
}
/* Debugging Function */
@@ -294,7 +294,7 @@ static void dump_spd_data(void)
for (dimm = 0; dimm < 8; dimm++) {
print_debug("SPD Data for DIMM ");
print_debug_hex8(dimm);
- print_debug("\r\n");
+ print_debug("\n");
val = get_spd_data(dimm, 0);
if (val == 0xff) {
@@ -302,7 +302,7 @@ static void dump_spd_data(void)
} else if (val == 0x80) {
regs = 128;
} else {
- print_debug("No DIMM present\r\n");
+ print_debug("No DIMM present\n");
regs = 0;
}
for (offset = 0; offset < regs; offset++) {
@@ -310,7 +310,7 @@ static void dump_spd_data(void)
print_debug_hex8(offset);
print_debug(" = 0x");
print_debug_hex8(get_spd_data(dimm, offset));
- print_debug("\r\n");
+ print_debug("\n");
}
}
}