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-rw-r--r--src/northbridge/amd/amdfam10/northbridge.c22
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mct_d.c11
2 files changed, 32 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index ced64aa65e..600fdf8596 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -1650,6 +1650,17 @@ static void detect_and_enable_probe_filter(device_t dev)
{
uint32_t dword;
+ uint8_t nvram;
+ uint8_t enable_probe_filter;
+
+ /* Check to see if the probe filter is allowed */
+ enable_probe_filter = 1;
+ if (get_option(&nvram, "probe_filter") == CB_SUCCESS)
+ enable_probe_filter = !!nvram;
+
+ if (!enable_probe_filter)
+ return;
+
uint8_t fam15h = 0;
uint8_t rev_gte_d = 0;
uint8_t dual_node = 0;
@@ -1810,6 +1821,17 @@ static void detect_and_enable_cache_partitioning(device_t dev)
uint8_t i;
uint32_t dword;
+ uint8_t nvram;
+ uint8_t enable_l3_cache_partitioning;
+
+ /* Check to see if cache partitioning is allowed */
+ enable_l3_cache_partitioning = 0;
+ if (get_option(&nvram, "l3_cache_partitioning") == CB_SUCCESS)
+ enable_l3_cache_partitioning = !!nvram;
+
+ if (!enable_l3_cache_partitioning)
+ return;
+
if (is_fam15h()) {
printk(BIOS_DEBUG, "Enabling L3 cache partitioning\n");
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index aad813a056..a6cc70f9f5 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -5559,6 +5559,14 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
mct_ExtMCTConfig_Dx(pDCTstat);
} else {
/* Family 15h CPUs */
+ uint8_t nvram;
+ uint8_t enable_experimental_memory_speed_boost;
+
+ /* Check to see if cache partitioning is allowed */
+ enable_experimental_memory_speed_boost = 0;
+ if (get_option(&nvram, "experimental_memory_speed_boost") == CB_SUCCESS)
+ enable_experimental_memory_speed_boost = !!nvram;
+
val = 0x0ce00f00; /* FlushWrOnStpGnt = 0x0 */
val |= 0x10 << 2; /* MctWrLimit = 0x10 */
val |= 0x1; /* DctWrLimit = 0x1 */
@@ -5572,7 +5580,8 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
val &= ~(0x7 << 8); /* CohPrefPrbLmt = 0x1 */
val |= (0x1 << 8);
val |= (0x1 << 12); /* EnSplitDctLimits = 0x1 */
- val |= (0x1 << 20); /* DblPrefEn = 0x1 */
+ if (enable_experimental_memory_speed_boost)
+ val |= (0x1 << 20); /* DblPrefEn = 0x1 */
val |= (0x7 << 22); /* PrefFourConf = 0x7 */
val |= (0x7 << 25); /* PrefFiveConf = 0x7 */
val &= ~(0xf << 28); /* DcqBwThrotWm = 0x0 */