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-rw-r--r--src/northbridge/intel/fsp_sandybridge/northbridge.c11
1 files changed, 9 insertions, 2 deletions
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c
index da27b25208..a95d7368b5 100644
--- a/src/northbridge/intel/fsp_sandybridge/northbridge.c
+++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c
@@ -243,9 +243,16 @@ static void pci_domain_set_resources(device_t dev)
add_fixed_resources(dev, 6);
assign_resources(dev->link_list);
+}
+
+unsigned long get_top_of_ram(void)
+{
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
- /* Leave some space for the HOB data above CBMem */
- set_top_of_ram((tomk - 2048) * 1024);
+ /* Base of TSEG is top of usable DRAM */
+ u32 tom = pci_read_config32(dev, TSEG) & ~(1UL << 0);
+ tom -= 0x200000; /* 2MB for FSP HOB */
+ return (unsigned long) tom;
}
/* TODO We could determine how many PCIe busses we need in