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-rw-r--r--src/northbridge/amd/agesa/family14/chip.h4
-rw-r--r--src/northbridge/amd/amdfam10/resourcemap.c4
-rw-r--r--src/northbridge/amd/amdht/h3gtopo.h2
-rw-r--r--src/northbridge/amd/amdmct/amddefs.h4
-rw-r--r--src/northbridge/amd/amdmct/mct/mct_d.c9
-rw-r--r--src/northbridge/amd/amdmct/mct/mct_d_gcc.c2
-rw-r--r--src/northbridge/amd/amdmct/mct/mctdqs_d.c4
-rw-r--r--src/northbridge/amd/amdmct/mct/mctecc_d.c2
-rw-r--r--src/northbridge/amd/amdmct/mct/mctmtr_d.c6
-rw-r--r--src/northbridge/amd/amdmct/mct/mctsrc.c2
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mct_d.c13
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mct_d.h2
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c6
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c4
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c6
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c6
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/s3utils.c2
-rw-r--r--src/northbridge/amd/lx/northbridgeinit.c2
-rw-r--r--src/northbridge/amd/lx/raminit.c4
-rw-r--r--src/northbridge/intel/e7505/e7505.h2
20 files changed, 44 insertions, 42 deletions
diff --git a/src/northbridge/amd/agesa/family14/chip.h b/src/northbridge/amd/agesa/family14/chip.h
index c3cd965c8b..211ee240ab 100644
--- a/src/northbridge/amd/agesa/family14/chip.h
+++ b/src/northbridge/amd/agesa/family14/chip.h
@@ -26,8 +26,8 @@ struct northbridge_amd_agesa_family14_config
*
* register "spdAddrLookup" = "
* { // Use 8-bit SPD addresses here
- * { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1
- * { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused)
+ * { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1
+ * { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused)
* }"
*
*/
diff --git a/src/northbridge/amd/amdfam10/resourcemap.c b/src/northbridge/amd/amdfam10/resourcemap.c
index be6f0ef062..5db6886e41 100644
--- a/src/northbridge/amd/amdfam10/resourcemap.c
+++ b/src/northbridge/amd/amdfam10/resourcemap.c
@@ -123,7 +123,7 @@ static void setup_default_resource_map(void)
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
* This field defines the upp adddress bits of a 40-bit
* address that defines the end of a memory-mapped
- * I/O region n
+ * I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
@@ -158,7 +158,7 @@ static void setup_default_resource_map(void)
* [ 7: 4] Reserved
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
* This field defines the upper address bits of a 40bit
- * address that defines the start of memory-mapped
+ * address that defines the start of memory-mapped
* I/O region i
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
diff --git a/src/northbridge/amd/amdht/h3gtopo.h b/src/northbridge/amd/amdht/h3gtopo.h
index 58673aaee3..7baba303dc 100644
--- a/src/northbridge/amd/amdht/h3gtopo.h
+++ b/src/northbridge/amd/amdht/h3gtopo.h
@@ -256,7 +256,7 @@ static u8 const amdHtTopologySevenTwistedLadder[] = {
0x00, 0x41, 0x30, 0x11, 0x00, 0x45, 0x32, 0xFF, 0x02, 0x44, 0x12, 0x55, 0x02, 0x44, // Node3
0x48, 0x22, 0x40, 0x33, 0x48, 0x22, 0x40, 0x33, 0x4C, 0xFF, 0x40, 0x32, 0x0C, 0x66, // Node4
0x00, 0x22, 0x04, 0x33, 0x00, 0x22, 0x04, 0x33, 0x00, 0x23, 0x0C, 0xFF, 0x00, 0x23, // Node5
- 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6
+ 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6
};
diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h
index 58f43f1500..03d9bb3477 100644
--- a/src/northbridge/amd/amdmct/amddefs.h
+++ b/src/northbridge/amd/amdmct/amddefs.h
@@ -71,10 +71,10 @@
#define AMD_DR_GT_D0 ((AMD_DR_Dx & ~(AMD_HY_D0)) | AMD_DR_Ex)
#define AMD_DR_ALL (AMD_DR_Ax | AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx | AMD_DR_Ex)
#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1 | AMD_PH_E0)
-#define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0))
+#define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0))
#define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0))
#define AMD_FAM10_REV_D (AMD_HY_D0 | AMD_HY_D1)
-#define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3)
+#define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3)
#define AMD_FAM10_C3 (AMD_RB_C3 | AMD_DA_C3)
#define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0)
#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2)
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index 8bee4344e7..4267e6d07c 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -3752,10 +3752,11 @@ void mct_SetDramConfigHi_D(struct DCTStatStruc *pDCTstat, u32 dct,
* Solution: From the bug report:
* 1. A software-initiated frequency change should be wrapped into the
* following sequence :
- * - a) Disable Compensation (F2[1, 0]9C_x08[30])
- * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines
- * c) Do frequency change
- * d) Enable Compensation (F2[1, 0]9C_x08[30])
+ * a) Disable Compensation (F2[1, 0]9C_x08[30])
+ * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in
+ * all the compensation engines
+ * c) Do frequency change
+ * d) Enable Compensation (F2[1, 0]9C_x08[30])
* 2. A software-initiated Disable Compensation should always be
* followed by step b) of the above steps.
* Silicon Status: Fixed In Rev B0
diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.c b/src/northbridge/amd/amdmct/mct/mct_d_gcc.c
index 59618f6cc0..d826fed96d 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.c
@@ -218,7 +218,7 @@ void ReadL18TestPattern(u32 addr_lo)
// set fs and use fs prefix to access the mem
__asm__ volatile (
"outb %%al, $0xed\n\t" /* _EXECFENCE */
- "movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line
+ "movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line
"movl %%fs:-64(%%esi), %%eax\n\t" //+1
"movl %%fs:(%%esi), %%eax\n\t" //+2
"movl %%fs:64(%%esi), %%eax\n\t" //+3
diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
index 71400071cf..9bb87bbb2a 100644
--- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
@@ -461,7 +461,7 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat,
continue;
}
- BanksPresent = 1; /* flag for at least one bank is present */
+ BanksPresent = 1; /* flag for at least one bank is present */
TestAddr = mct_GetMCTSysAddr_D(pMCTstat, pDCTstat, pDCTstat->Channel, ChipSel, &valid);
if (!valid) {
print_debug_dqs("\t\t\t\tAddress not supported on current CS ", TestAddr, 4);
@@ -762,7 +762,7 @@ static u8 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatS
test_buf += 2;
}
- bytelane = 0; /* bytelane counter */
+ bytelane = 0; /* bytelane counter */
bitmap = 0xFF; /* bytelane test bitmap, 1 = pass */
for (i = 0; i < (9 * 64 / 4); i++) { /* sizeof testpattern. /4 due to next loop */
value = read32_fs(addr_lo);
diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c
index 9b22c84449..18774ebe7a 100644
--- a/src/northbridge/amd/amdmct/mct/mctecc_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c
@@ -96,7 +96,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
OB_ECCRedir = mctGet_NVbits(NV_ECCRedir); /* ECC Redirection */
- OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */
+ OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */
OF_ScrubCTL = 0; /* Scrub CTL for Dcache, L2, and dram */
nvbits = mctGet_NVbits(NV_DCBKScrub);
diff --git a/src/northbridge/amd/amdmct/mct/mctmtr_d.c b/src/northbridge/amd/amdmct/mct/mctmtr_d.c
index deb0f8a2e5..1e47ab4c39 100644
--- a/src/northbridge/amd/amdmct/mct/mctmtr_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctmtr_d.c
@@ -36,11 +36,11 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
/* Set temporary top of memory from Node structure data.
* Adjust temp top of memory down to accommodate 32-bit IO space.
* Bottom40bIO = top of memory, right justified 8 bits
- * (defines dram versus IO space type)
+ * (defines dram versus IO space type)
* Bottom32bIO = sub 4GB top of memory, right justified 8 bits
- * (defines dram versus IO space type)
+ * (defines dram versus IO space type)
* Cache32bTOP = sub 4GB top of WB cacheable memory,
- * right justified 8 bits
+ * right justified 8 bits
*/
val = mctGet_NVbits(NV_BottomIO);
diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c
index 60857f4052..a29f8eb42e 100644
--- a/src/northbridge/amd/amdmct/mct/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct/mctsrc.c
@@ -450,7 +450,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat,
}
if (!_SSE2) {
cr4 = read_cr4();
- cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
+ cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
write_cr4(cr4);
}
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index da803ff627..7421c18a69 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -2346,7 +2346,7 @@ void set_2t_configuration(struct MCTStatStruc *pMCTstat,
enable_slow_access_mode = 1;
}
- reg = 0x94; /* DRAM Configuration High */
+ reg = 0x94; /* DRAM Configuration High */
dword = Get_NB32_DCT(dev, dct, reg);
if (enable_slow_access_mode)
dword |= (0x1 << 20); /* Set 2T CMD mode */
@@ -2539,7 +2539,7 @@ static void set_cc6_save_enable(struct MCTStatStruc *pMCTstat,
uint32_t dword;
dword = Get_NB32(pDCTstat->dev_dct, 0x118);
- dword &= ~(0x1 << 18); /* CC6SaveEn = enable */
+ dword &= ~(0x1 << 18); /* CC6SaveEn = enable */
dword |= (enable & 0x1) << 18;
Set_NB32(pDCTstat->dev_dct, 0x118, dword);
}
@@ -7908,10 +7908,11 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat,
* Solution: From the bug report:
* 1. A software-initiated frequency change should be wrapped into the
* following sequence :
- * - a) Disable Compensation (F2[1, 0]9C_x08[30])
- * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines
- * c) Do frequency change
- * d) Enable Compensation (F2[1, 0]9C_x08[30])
+ * a) Disable Compensation (F2[1, 0]9C_x08[30])
+ * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in
+ * all the compensation engines
+ * c) Do frequency change
+ * d) Enable Compensation (F2[1, 0]9C_x08[30])
* 2. A software-initiated Disable Compensation should always be
* followed by step b) of the above steps.
* Silicon Status: Fixed In Rev B0
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
index d4b37921c4..a02f49b5c6 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
@@ -134,7 +134,7 @@
#define MemClkFreqVal ((is_fam15h())?7:3) /* func 2, offset 94h, bit 3 or 7*/
#define RDqsEn 12 /* func 2, offset 94h, bit 12*/
#define DisDramInterface 14 /* func 2, offset 94h, bit 14*/
-#define PowerDownEn 15 /* func 2, offset 94h, bit 15*/
+#define PowerDownEn 15 /* func 2, offset 94h, bit 15*/
#define DctAccessWrite 30 /* func 2, offset 98h, bit 30*/
#define DctAccessDone 31 /* func 2, offset 98h, bit 31*/
#define MemClrStatus 0 /* func 2, offset A0h, bit 0*/
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index f751733f73..9b7481717d 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -1102,7 +1102,7 @@ void read_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat,
dword = Get_NB32_DCT(dev, dct, 0x270);
dword &= ~(0x7ffff); /* DataPrbsSeed = 55555 */
-// dword |= (0x55555);
+// dword |= (0x55555);
dword |= (0x44443); /* Use AGESA seed */
Set_NB32_DCT(dev, dct, 0x270, dword);
@@ -1199,7 +1199,7 @@ void write_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat,
dword = Get_NB32_DCT(dev, dct, 0x270);
dword &= ~(0x7ffff); /* DataPrbsSeed = 55555 */
-// dword |= (0x55555);
+// dword |= (0x55555);
dword |= (0x44443); /* Use AGESA seed */
Set_NB32_DCT(dev, dct, 0x270, dword);
@@ -1633,7 +1633,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat,
uint8_t lane_training_success[MAX_BYTE_LANES];
uint8_t dqs_results_array[1024];
- uint16_t ren_step = 0x40;
+ uint16_t ren_step = 0x40;
uint32_t index_reg = 0x98;
uint32_t dev = pDCTstat->dev_dct;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
index 9aad96cfbc..31c23b9445 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
@@ -115,12 +115,12 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
OB_ECCRedir = mctGet_NVbits(NV_ECCRedir); /* ECC Redirection */
- OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */
+ OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */
OF_ScrubCTL = 0; /* Scrub CTL for Dcache, L2, and dram */
if (!is_fam15h()) {
nvbits = mctGet_NVbits(NV_DCBKScrub);
- /* mct_AdjustScrub_D(pDCTstatA, &nvbits); */ /* Need not adjust */
+ /* mct_AdjustScrub_D(pDCTstatA, &nvbits); */ /* Need not adjust */
OF_ScrubCTL |= (u32) nvbits << 16;
nvbits = mctGet_NVbits(NV_L2BKScrub);
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c
index 8a1f7362a8..2bf85622e6 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c
@@ -40,11 +40,11 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
/* Set temporary top of memory from Node structure data.
* Adjust temp top of memory down to accommodate 32-bit IO space.
* Bottom40bIO = top of memory, right justified 8 bits
- * (defines dram versus IO space type)
+ * (defines dram versus IO space type)
* Bottom32bIO = sub 4GB top of memory, right justified 8 bits
- * (defines dram versus IO space type)
+ * (defines dram versus IO space type)
* Cache32bTOP = sub 4GB top of WB cacheable memory,
- * right justified 8 bits
+ * right justified 8 bits
*/
val = mctGet_NVbits(NV_BottomIO);
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
index 984f604135..7c3781fb40 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
@@ -1002,7 +1002,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat,
}
if (!_SSE2) {
cr4 = read_cr4();
- cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
+ cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
write_cr4(cr4);
}
@@ -1505,7 +1505,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
}
if (!_SSE2) {
cr4 = read_cr4();
- cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
+ cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
write_cr4(cr4);
}
@@ -1725,7 +1725,7 @@ void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat,
}
if (!_SSE2) {
cr4 = read_cr4();
- cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
+ cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
write_cr4(cr4);
}
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
index a351e8dfb5..84e26eadea 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
@@ -707,7 +707,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
* For now, skip restoration...
*/
// for (i = 0; i < 8; i++)
- // wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]);
+ // wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]);
wrmsr_uint64_t(0x000002ff, data->msr000002ff);
wrmsr_uint64_t(0xc0010010, data->msrc0010010);
wrmsr_uint64_t(0xc001001a, data->msrc001001a);
diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c
index b8a67ee2f8..6c2efb320c 100644
--- a/src/northbridge/amd/lx/northbridgeinit.c
+++ b/src/northbridge/amd/lx/northbridgeinit.c
@@ -594,7 +594,7 @@ static void rom_shadow_settings(void)
* ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of ROM chipselect area
* DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst.
* SYSTOP(27:8) = top of system memory
- * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough
+ * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough
*
***************************************************************************/
#define SYSMEM_RCONF_WRITETHROUGH 8
diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
index 3be0248571..ab5c70f09f 100644
--- a/src/northbridge/amd/lx/raminit.c
+++ b/src/northbridge/amd/lx/raminit.c
@@ -419,8 +419,8 @@ static void set_latencies(void)
/* tRC = tRP + tRAS */
dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) +
- ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07))
- << CF8F_LOWER_ACT2ACTREF_SHIFT;
+ ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07))
+ << CF8F_LOWER_ACT2ACTREF_SHIFT;
msr = rdmsr(MC_CF8F_DATA);
msr.lo &= 0xF00000FF;
diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h
index 5ceeacceaf..b80d8a8a52 100644
--- a/src/northbridge/intel/e7505/e7505.h
+++ b/src/northbridge/intel/e7505/e7505.h
@@ -26,7 +26,7 @@
#define SMRBASE 0x14 /* System Memory RCOMP Base Address Register, 32 bit? */
#define MCHCFGNS 0x52 /* MCH (scrubber) configuration register, 16 bit */
-#define PAM_0 0x59
+#define PAM_0 0x59
#define DRB_ROW_0 0x60 /* DRAM Row Boundary register, 8 bit */
#define DRB_ROW_1 0x61
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 19:18:07 +0000