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-rw-r--r--src/northbridge/via/vx900/raminit.h1
-rw-r--r--src/northbridge/via/vx900/raminit_ddr3.c6
2 files changed, 5 insertions, 2 deletions
diff --git a/src/northbridge/via/vx900/raminit.h b/src/northbridge/via/vx900/raminit.h
index c599c0fee8..0fd626fda3 100644
--- a/src/northbridge/via/vx900/raminit.h
+++ b/src/northbridge/via/vx900/raminit.h
@@ -71,6 +71,7 @@ typedef struct vx900_delay_calib_st {
typedef struct ramctr_timing_st {
enum spd_memory_type dram_type;
+ enum spd_dimm_type dimm_type;
u16 cas_supported;
/* tLatencies are in units of ns, scaled by x256 */
u32 tCK;
diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c
index 3979466bf0..e6dace3b40 100644
--- a/src/northbridge/via/vx900/raminit_ddr3.c
+++ b/src/northbridge/via/vx900/raminit_ddr3.c
@@ -369,9 +369,11 @@ static void dram_find_common_params(const dimm_info * dimms,
if (valid_dimms == 1) {
/* First DIMM defines the type of DIMM */
ctrl->dram_type = dimm->dram_type;
+ ctrl->dimm_type = dimm->dimm_type;
} else {
/* Check if we have mismatched DIMMs */
- if (ctrl->dram_type != dimm->dram_type)
+ if (ctrl->dram_type != dimm->dram_type
+ || ctrl->dimm_type != dimm->dimm_type)
die("Mismatched DIMM Types");
}
/* Find all possible CAS combinations */
@@ -705,7 +707,7 @@ static void vx900_dram_freq(ramctr_timing * ctrl)
pci_mod_config8(MCU, 0x6b, 0x80, 0x00);
/* Step 8 - If we have registered DIMMs, we need to set bit[0] */
- if (dimm_is_registered(ctrl->dram_type)) {
+ if (dimm_is_registered(ctrl->dimm_type)) {
printram("Enabling RDIMM support in memory controller\n");
pci_mod_config8(MCU, 0x6c, 0x00, 0x01);
}