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-rw-r--r--src/northbridge/amd/agesa/family10/northbridge.c38
-rw-r--r--src/northbridge/amd/agesa/family12/northbridge.c24
-rw-r--r--src/northbridge/amd/agesa/family14/northbridge.c24
-rw-r--r--src/northbridge/amd/agesa/family15/northbridge.c24
-rw-r--r--src/northbridge/amd/amdfam10/amdfam10.h6
-rw-r--r--src/northbridge/amd/amdfam10/conf.c10
-rw-r--r--src/northbridge/amd/amdfam10/debug.c2
-rw-r--r--src/northbridge/amd/amdfam10/early_ht.c4
-rw-r--r--src/northbridge/amd/amdfam10/northbridge.c54
-rw-r--r--src/northbridge/amd/amdfam10/reset_test.c2
-rw-r--r--src/northbridge/amd/amdht/ht_wrapper.c2
-rw-r--r--src/northbridge/amd/amdk8/amdk8.h2
-rw-r--r--src/northbridge/amd/amdk8/coherent_ht.c24
-rw-r--r--src/northbridge/amd/amdk8/debug.c2
-rw-r--r--src/northbridge/amd/amdk8/incoherent_ht.c12
-rw-r--r--src/northbridge/amd/amdk8/misc_control.c2
-rw-r--r--src/northbridge/amd/amdk8/northbridge.c42
-rw-r--r--src/northbridge/amd/amdk8/raminit.c4
-rw-r--r--src/northbridge/amd/amdk8/raminit_f.c8
-rw-r--r--src/northbridge/amd/amdk8/raminit_f_dqs.c6
-rw-r--r--src/northbridge/amd/amdmct/wrappers/mcti_d.c10
-rw-r--r--src/northbridge/amd/gx1/northbridge.c4
-rw-r--r--src/northbridge/amd/gx2/northbridge.c4
-rw-r--r--src/northbridge/amd/lx/northbridge.c4
-rw-r--r--src/northbridge/intel/e7501/northbridge.c4
-rw-r--r--src/northbridge/intel/e7505/northbridge.c4
-rw-r--r--src/northbridge/intel/e7520/northbridge.c4
-rw-r--r--src/northbridge/intel/e7525/northbridge.c4
-rw-r--r--src/northbridge/intel/i3100/northbridge.c4
-rw-r--r--src/northbridge/intel/i3100/raminit.c2
-rw-r--r--src/northbridge/intel/i440bx/northbridge.c4
-rw-r--r--src/northbridge/intel/i440lx/northbridge.c4
-rw-r--r--src/northbridge/intel/i82810/northbridge.c4
-rw-r--r--src/northbridge/intel/i82830/northbridge.c4
-rw-r--r--src/northbridge/intel/i855/northbridge.c4
-rw-r--r--src/northbridge/intel/i945/northbridge.c4
-rw-r--r--src/northbridge/intel/sandybridge/northbridge.c4
-rw-r--r--src/northbridge/intel/sch/northbridge.c4
-rw-r--r--src/northbridge/rdc/r8610/northbridge.c4
-rw-r--r--src/northbridge/via/cn400/northbridge.c4
-rw-r--r--src/northbridge/via/cn700/northbridge.c4
-rw-r--r--src/northbridge/via/cx700/northbridge.c4
-rw-r--r--src/northbridge/via/vt8601/northbridge.c4
-rw-r--r--src/northbridge/via/vt8623/northbridge.c4
-rw-r--r--src/northbridge/via/vx800/examples/chipset_init.c4
45 files changed, 198 insertions, 198 deletions
diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c
index ee02f0d87a..7b73987e40 100644
--- a/src/northbridge/amd/agesa/family10/northbridge.c
+++ b/src/northbridge/amd/agesa/family10/northbridge.c
@@ -31,7 +31,7 @@
#include <cpu/x86/lapic.h>
#include <cbmem.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <pc80/mc146818rtc.h>
#endif
@@ -70,7 +70,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid)
dram_base_mask_t d;
dev = __f1_dev[0];
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
/* I will use ext space only for simple */
pci_write_config32(dev, 0x110, nodeid | (1<<28)); // [47:27] at [28:8]
d.mask = pci_read_config32(dev, 0x114); // enable is bit 0
@@ -551,7 +551,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource = amdfam10_find_iopair(dev, nodeid, link);
if (resource) {
u32 align;
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
if((resource->index & 0x1fff) == 0x1110) { // ext
align = 8;
}
@@ -577,7 +577,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
resource->flags |= IORESOURCE_BRIDGE;
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
if ((resource->index & 0x1fff) == 0x1110) { // ext
normalize_resource(resource);
}
@@ -594,7 +594,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource->gran = log2(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
if ((resource->index & 0x1fff) == 0x1110) { // ext
normalize_resource(resource);
}
@@ -677,7 +677,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid)
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1
+#if CONFIG_MULTIPLE_VGA_ADAPTERS
extern device_t vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
@@ -806,7 +806,7 @@ static void amdfam10_domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
-#if CONFIG_PCI_64BIT_PREF_MEM == 0
+#if !CONFIG_PCI_64BIT_PREF_MEM
pci_domain_read_resources(dev);
#else
struct bus *link;
@@ -908,7 +908,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
}
#endif
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
extern uint64_t uma_memory_base, uma_memory_size;
static void add_uma_resource(struct device *dev, int index)
@@ -926,7 +926,7 @@ static void add_uma_resource(struct device *dev, int index)
static void amdfam10_domain_set_resources(device_t dev)
{
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
struct resource *io, *mem1, *mem2;
struct resource *res;
#endif
@@ -939,7 +939,7 @@ static void amdfam10_domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
for (link = dev->link_list; link; link = link->next) {
/* Now reallocate the pci resources memory with the
@@ -1054,10 +1054,10 @@ static void amdfam10_domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
#else
high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
@@ -1079,19 +1079,19 @@ static void amdfam10_domain_set_resources(device_t dev)
}
}
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
/* Deduct uma memory before reporting because
* this is what the mtrr code expects */
sizek -= uma_memory_size / 1024;
#endif
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
i, mmio_basek, basek, limitk);
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
#else
high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
@@ -1101,7 +1101,7 @@ static void amdfam10_domain_set_resources(device_t dev)
#endif
}
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
add_uma_resource(dev, 7);
#endif
@@ -1121,7 +1121,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max)
for (reg = 0xe0; reg <= 0xec; reg += 4) {
f1_write_config32(reg, 0);
}
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
// all nodes
for (i = 0; i< sysconf.nodes; i++) {
int index;
@@ -1270,7 +1270,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
}
disable_siblings = !CONFIG_LOGICAL_CPUS;
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
get_option(&disable_siblings, "multi_core");
#endif
@@ -1376,7 +1376,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
* otherwise the device under it will not be scanned
*/
int linknum;
-#if CONFIG_HT3_SUPPORT==1
+#if CONFIG_HT3_SUPPORT
linknum = 8;
#else
linknum = 4;
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index a3afecb217..efc0a489d8 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -222,7 +222,7 @@ static void amdfam12_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource = amdfam12_find_iopair(dev, nodeid, link);
if (resource) {
u32 align;
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
if((resource->index & 0x1fff) == 0x1110) { // ext
align = 8;
}
@@ -248,7 +248,7 @@ static void amdfam12_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
resource->flags |= IORESOURCE_BRIDGE;
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
if((resource->index & 0x1fff) == 0x1110) { // ext
normalize_resource(resource);
}
@@ -265,7 +265,7 @@ static void amdfam12_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource->gran = log2(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
if((resource->index & 0x1fff) == 0x1110) { // ext
normalize_resource(resource);
}
@@ -338,7 +338,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
}
#endif
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
extern uint64_t uma_memory_base, uma_memory_size;
static void add_uma_resource(struct device *dev, int index)
@@ -525,7 +525,7 @@ static void domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
-#if CONFIG_PCI_64BIT_PREF_MEM == 0
+#if !CONFIG_PCI_64BIT_PREF_MEM
//- pci_domain_read_resources(dev);
struct resource *resource;
@@ -574,7 +574,7 @@ static void domain_set_resources(device_t dev)
printk(BIOS_DEBUG, " amsr - incoming dev = %08lx\n",dev);
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
struct resource *io, *mem1, *mem2;
struct resource *res;
#endif
@@ -587,7 +587,7 @@ static void domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n");
for(link = dev->link_list; link; link = link->next) {
@@ -711,10 +711,10 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08x, basek=%08x, limitk=%08x\n", mmio_bas
ram_resource(dev, idx, basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
#else
high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
@@ -740,12 +740,12 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08x, basek=%08x, limitk=%08x\n", mmio_bas
ram_resource(dev, (idx | 0), basek, sizek);
idx += 0x10;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
0, mmio_basek, basek, limitk);
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
printk(BIOS_DEBUG, " adsr - uma_memory_base = %x.\n",uma_memory_base);
#else
@@ -758,7 +758,7 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08x, basek=%08x, limitk=%08x\n", mmio_bas
printk(BIOS_DEBUG, " adsr - mmio_basek = %x.\n",mmio_basek);
printk(BIOS_DEBUG, " adsr - high_tables_size = %x.\n",high_tables_size);
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
printk(BIOS_DEBUG, "adsr - adding uma resource.\n");
add_uma_resource(dev, 7);
#endif
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index 2647814389..f7c3b8e11f 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -210,7 +210,7 @@ static void amdfam14_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource = amdfam14_find_iopair(dev, nodeid, link);
if (resource) {
u32 align;
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
if ((resource->index & 0x1fff) == 0x1110) { // ext
align = 8;
} else
@@ -235,7 +235,7 @@ static void amdfam14_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
resource->flags |= IORESOURCE_BRIDGE;
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
if ((resource->index & 0x1fff) == 0x1110) { // ext
normalize_resource(resource);
}
@@ -252,7 +252,7 @@ static void amdfam14_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource->gran = log2(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
if ((resource->index & 0x1fff) == 0x1110) { // ext
normalize_resource(resource);
}
@@ -326,7 +326,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
}
#endif
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
extern uint64_t uma_memory_base, uma_memory_size;
static void add_uma_resource(struct device *dev, int index)
@@ -508,7 +508,7 @@ static void domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
-#if CONFIG_PCI_64BIT_PREF_MEM == 0
+#if !CONFIG_PCI_64BIT_PREF_MEM
pci_domain_read_resources(dev);
#else
struct bus *link;
@@ -538,7 +538,7 @@ static void domain_set_resources(device_t dev)
printk(BIOS_DEBUG, "\nFam14h - domain_set_resources.\n");
printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev);
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
struct resource *io, *mem1, *mem2;
struct resource *res;
#endif
@@ -551,7 +551,7 @@ static void domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n");
for (link = dev->link_list; link; link = link->next) {
@@ -685,10 +685,10 @@ static void domain_set_resources(device_t dev)
pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
if (high_tables_base == 0) {
/* Leave some space for ACPI, PIRQ and MP tables */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
#else
high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
@@ -712,13 +712,13 @@ static void domain_set_resources(device_t dev)
ram_resource(dev, (idx | 0), basek, sizek);
idx += 0x10;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
printk(BIOS_DEBUG,
"%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0,
mmio_basek, basek, limitk);
if (high_tables_base == 0) {
/* Leave some space for ACPI, PIRQ and MP tables */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
printk(BIOS_DEBUG, " adsr - uma_memory_base = %llx.\n", uma_memory_base);
#else
@@ -732,7 +732,7 @@ static void domain_set_resources(device_t dev)
printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n",
high_tables_size);
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
printk(BIOS_DEBUG, "adsr - adding uma resource.\n");
add_uma_resource(dev, 7);
#endif
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c
index d1a322ca6c..130086eb91 100644
--- a/src/northbridge/amd/agesa/family15/northbridge.c
+++ b/src/northbridge/amd/agesa/family15/northbridge.c
@@ -406,7 +406,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid)
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1
+#if CONFIG_MULTIPLE_VGA_ADAPTERS
extern device_t vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
@@ -540,7 +540,7 @@ static void domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
-#if CONFIG_PCI_64BIT_PREF_MEM == 0
+#if !CONFIG_PCI_64BIT_PREF_MEM
pci_domain_read_resources(dev);
@@ -626,7 +626,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
}
#endif
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
extern uint64_t uma_memory_base, uma_memory_size;
static void add_uma_resource(struct device *dev, int index)
{
@@ -644,7 +644,7 @@ static void add_uma_resource(struct device *dev, int index)
static void domain_set_resources(device_t dev)
{
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
struct resource *io, *mem1, *mem2;
struct resource *res;
#endif
@@ -657,7 +657,7 @@ static void domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
for (link = dev->link_list; link; link = link->next) {
/* Now reallocate the pci resources memory with the
@@ -773,10 +773,10 @@ static void domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
#else
high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
@@ -798,19 +798,19 @@ static void domain_set_resources(device_t dev)
}
}
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
/* Deduct uma memory before reporting because
* this is what the mtrr code expects */
sizek -= uma_memory_size / 1024;
#endif
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
i, mmio_basek, basek, limitk);
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
#else
high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
@@ -820,7 +820,7 @@ static void domain_set_resources(device_t dev)
#endif
}
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
add_uma_resource(dev, 7);
#endif
@@ -1022,7 +1022,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
* otherwise the device under it will not be scanned
*/
int linknum;
-#if CONFIG_HT3_SUPPORT==1
+#if CONFIG_HT3_SUPPORT
linknum = 8;
#else
linknum = 4;
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index 99518065de..712c98638e 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -976,7 +976,7 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
#include "raminit.h"
-#if CONFIG_AMDMCT == 0
+#if !CONFIG_AMDMCT
//struct definitions
@@ -1034,7 +1034,7 @@ struct nodes_info_t {
} __attribute__((packed));
/* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and coreboot_ram stage. and coreboot_ram may be running at 64bit later.*/
-#if CONFIG_AMDMCT == 0
+#if !CONFIG_AMDMCT
//#define MEM_CS_COPY 1
#define MEM_CS_COPY NODE_NUMS
@@ -1102,7 +1102,7 @@ struct sys_info {
device_t get_node_pci(u32 nodeid, u32 fn);
#endif
-#if CONFIG_AMDMCT == 0
+#if !CONFIG_AMDMCT
#ifdef __PRE_RAM__
static void soft_reset(void);
diff --git a/src/northbridge/amd/amdfam10/conf.c b/src/northbridge/amd/amdfam10/conf.c
index adfff0f6e3..d8c161fc3d 100644
--- a/src/northbridge/amd/amdfam10/conf.c
+++ b/src/northbridge/amd/amdfam10/conf.c
@@ -38,7 +38,7 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
dev = __f1_dev[0];
#endif
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
// I will use ext space only for simple
pci_write_config32(dev, 0x110, nodeid | (1<<28)); // [47:27] at [28:8]
d.mask = pci_read_config32(dev, 0x114); // enable is bit 0
@@ -61,12 +61,12 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
return d;
}
-#if CONFIG_AMDMCT == 0
+#if !CONFIG_AMDMCT
static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes)
{
u32 i;
device_t dev;
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
// I will use ext space only for simple
u32 d_base_i, d_base_d, d_mask_i, d_mask_d;
d_base_i = nodeid | (0<<28);
@@ -95,7 +95,7 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes)
dev = __f1_dev[i];
#endif
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
// I will use ext space only for simple
pci_write_config32(dev, 0x110, d_base_i);
pci_write_config32(dev, 0x114, d_base_d); //[47:27] at [28:8];
@@ -120,7 +120,7 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes)
}
#endif
-#if CONFIG_AMDMCT == 0
+#if !CONFIG_AMDMCT
static void set_DctSelBaseAddr(u32 i, u32 sel_m)
{
device_t dev;
diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c
index 2dc54275fd..c6f7c780a9 100644
--- a/src/northbridge/amd/amdfam10/debug.c
+++ b/src/northbridge/amd/amdfam10/debug.c
@@ -33,7 +33,7 @@ static inline void print_debug_addr(const char *str, void *val)
static void print_debug_pci_dev(u32 dev)
{
-#if CONFIG_PCI_BUS_SEGN_BITS==0
+#if !CONFIG_PCI_BUS_SEGN_BITS
printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
#else
printk(BIOS_DEBUG, "PCI: %04x:%02x:%02x.%02x", (dev>>28) & 0x0f, (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c
index 58f2cddb36..bbf6b86ac9 100644
--- a/src/northbridge/amd/amdfam10/early_ht.c
+++ b/src/northbridge/amd/amdfam10/early_ht.c
@@ -21,7 +21,7 @@
// mmconf is not ready yet
static void set_bsp_node_CHtExtNodeCfgEn(void)
{
-#if CONFIG_EXT_RT_TBL_SUPPORT == 1
+#if CONFIG_EXT_RT_TBL_SUPPORT
u32 dword;
dword = pci_io_read_config32(PCI_DEV(0, 0x18, 0), 0x68);
dword |= (1<<27) | (1<<25);
@@ -112,7 +112,7 @@ static void enumerate_ht_chain(void)
real_last_pos = pos;
ht_dev_num++ ;
#endif
- #if CONFIG_HT_CHAIN_END_UNITID_BASE == 0
+ #if !CONFIG_HT_CHAIN_END_UNITID_BASE
if (!next_unitid)
goto out;
#endif
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 89bd6733ce..0e80c71324 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -31,7 +31,7 @@
#include <cpu/x86/lapic.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#include <pc80/mc146818rtc.h>
#endif
@@ -161,7 +161,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 l
#endif
u32 max_devfn;
-#if CONFIG_HT3_SUPPORT==1
+#if CONFIG_HT3_SUPPORT
if(is_sublink1) {
u32 regpos;
u32 reg;
@@ -192,7 +192,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 l
*/
ht_c_index = get_ht_c_index(nodeid, link_num, &sysconf);
-#if CONFIG_EXT_CONF_SUPPORT == 0
+#if !CONFIG_EXT_CONF_SUPPORT
if(ht_c_index>=4) return max;
#endif
@@ -316,7 +316,7 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned max)
#endif
offset_unitid = 0;
#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
- #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+ #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
if((nodeid == 0) && (sblink == link->link_num))
#endif
offset_unitid = 1;
@@ -434,7 +434,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource = amdfam10_find_iopair(dev, nodeid, link);
if (resource) {
u32 align;
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
if((resource->index & 0x1fff) == 0x1110) { // ext
align = 8;
}
@@ -460,7 +460,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
resource->flags |= IORESOURCE_BRIDGE;
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
if((resource->index & 0x1fff) == 0x1110) { // ext
normalize_resource(resource);
}
@@ -477,7 +477,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource->gran = log2(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
if((resource->index & 0x1fff) == 0x1110) { // ext
normalize_resource(resource);
}
@@ -560,7 +560,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid)
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1
+#if CONFIG_MULTIPLE_VGA_ADAPTERS
extern device_t vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
@@ -664,7 +664,7 @@ static void amdfam10_domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
-#if CONFIG_PCI_64BIT_PREF_MEM == 0
+#if !CONFIG_PCI_64BIT_PREF_MEM
pci_domain_read_resources(dev);
#else
struct bus *link;
@@ -762,7 +762,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
// WHY this check? CONFIG_AMDMCT is enabled on all Fam10 boards.
// Does it make sense not to?
-#if CONFIG_AMDMCT == 0
+#if !CONFIG_AMDMCT
static void disable_hoist_memory(unsigned long hole_startk, int node_id)
{
int i;
@@ -843,11 +843,11 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id)
#endif
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
extern uint64_t uma_memory_base, uma_memory_size;
static void add_uma_resource(struct device *dev, int index)
@@ -865,7 +865,7 @@ static void add_uma_resource(struct device *dev, int index)
static void amdfam10_domain_set_resources(device_t dev)
{
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
struct resource *io, *mem1, *mem2;
struct resource *res;
#endif
@@ -878,7 +878,7 @@ static void amdfam10_domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
for(link = dev->link_list; link; link = link->next) {
/* Now reallocate the pci resources memory with the
@@ -960,7 +960,7 @@ static void amdfam10_domain_set_resources(device_t dev)
reset_memhole = 0;
}
- #if CONFIG_AMDMCT == 0
+ #if !CONFIG_AMDMCT
//mmio_basek = 3*1024*1024; // for debug to meet boundary
if(reset_memhole) {
@@ -975,7 +975,7 @@ static void amdfam10_domain_set_resources(device_t dev)
disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
}
- #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
+ #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
// We need to double check if the mmio_basek is valid for hole
// setting, if it is equal to basek, we need to decrease it some
resource_t basek_pri;
@@ -1031,10 +1031,10 @@ static void amdfam10_domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
#else
high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
@@ -1045,7 +1045,7 @@ static void amdfam10_domain_set_resources(device_t dev)
}
#endif
}
- #if CONFIG_AMDMCT == 0
+ #if !CONFIG_AMDMCT
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
if(reset_memhole) {
struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
@@ -1067,19 +1067,19 @@ static void amdfam10_domain_set_resources(device_t dev)
}
}
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
/* Deduct uma memory before reporting because
* this is what the mtrr code expects */
sizek -= uma_memory_size / 1024;
#endif
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
i, mmio_basek, basek, limitk);
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
#else
high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
@@ -1089,7 +1089,7 @@ static void amdfam10_domain_set_resources(device_t dev)
#endif
}
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
add_uma_resource(dev, 7);
#endif
@@ -1109,7 +1109,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max)
for(reg = 0xe0; reg <= 0xec; reg += 4) {
f1_write_config32(reg, 0);
}
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
// all nodes
for(i = 0; i< sysconf.nodes; i++) {
int index;
@@ -1187,7 +1187,7 @@ static void sysconf_init(device_t dev) // first node
sysconf.bsp_apicid = lapicid();
sysconf.apicid_offset = sysconf.bsp_apicid;
-#if (CONFIG_ENABLE_APIC_EXT_ID == 1)
+#if CONFIG_ENABLE_APIC_EXT_ID
if (pci_read_config32(dev, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST))
{
sysconf.enabled_apic_ext_id = 1;
@@ -1265,7 +1265,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
}
disable_siblings = !CONFIG_LOGICAL_CPUS;
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
get_option(&disable_siblings, "multi_core");
#endif
@@ -1371,7 +1371,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
* otherwise the device under it will not be scanned
*/
int linknum;
-#if CONFIG_HT3_SUPPORT==1
+#if CONFIG_HT3_SUPPORT
linknum = 8;
#else
linknum = 4;
diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c
index c48fca630c..f1f22cbf35 100644
--- a/src/northbridge/amd/amdfam10/reset_test.c
+++ b/src/northbridge/amd/amdfam10/reset_test.c
@@ -127,7 +127,7 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b
}
}
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
// let's check that in extend space
// use the nodeid extend space to find out the bus for the linkn
u32 tempreg;
diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c
index 32908c4936..ff444d5225 100644
--- a/src/northbridge/amd/amdht/ht_wrapper.c
+++ b/src/northbridge/amd/amdht/ht_wrapper.c
@@ -28,7 +28,7 @@
*/
/* Single CPU system? */
-#if (CONFIG_MAX_PHYSICAL_CPUS == 1)
+#if CONFIG_MAX_PHYSICAL_CPUS
#define HT_BUILD_NC_ONLY 1
#endif
diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h
index e353edc479..5aa3b31fbf 100644
--- a/src/northbridge/amd/amdk8/amdk8.h
+++ b/src/northbridge/amd/amdk8/amdk8.h
@@ -2,7 +2,7 @@
#define AMDK8_H
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
#include "f.h"
#else
#include "pre_f.h"
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index a262686f87..636114df15 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -160,7 +160,7 @@ static void disable_probes(void)
#if 0
static void enable_apic_ext_id(u8 node)
{
-#if CONFIG_ENABLE_APIC_EXT_ID==1
+#if CONFIG_ENABLE_APIC_EXT_ID
#warning "FIXME Is the right place to enable apic ext id here?"
u32 val;
@@ -284,8 +284,8 @@ static uint16_t read_freq_cap(device_t dev, uint8_t pos)
freq_cap = pci_read_config16(dev, pos);
freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
-#if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1
- #if CONFIG_K8_REV_F_SUPPORT == 0
+#if CONFIG_K8_HT_FREQ_1G_SUPPORT
+ #if !CONFIG_K8_REV_F_SUPPORT
if (!is_cpu_pre_e0())
#endif
{
@@ -665,7 +665,7 @@ static void setup_remote_row_indirect_group(const u8 *conn, int num)
static void setup_uniprocessor(void)
{
print_spew("Enabling UP settings\n");
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3;
if (tmp>0) return;
#endif
@@ -1574,7 +1574,7 @@ static void clear_dead_routes(unsigned nodes)
}
#endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
static unsigned verify_dualcore(unsigned nodes)
{
unsigned node, totalcpus, tmp;
@@ -1593,10 +1593,10 @@ static unsigned verify_dualcore(unsigned nodes)
static void coherent_ht_finalize(unsigned nodes)
{
unsigned node;
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
int rev_a0;
#endif
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
unsigned total_cpus;
if (read_option(multi_core, 0) == 0) { /* multi_core */
@@ -1614,7 +1614,7 @@ static void coherent_ht_finalize(unsigned nodes)
*/
print_spew("coherent_ht_finalize\n");
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
rev_a0 = is_cpu_rev_a0();
#endif
for (node = 0; node < nodes; node++) {
@@ -1625,7 +1625,7 @@ static void coherent_ht_finalize(unsigned nodes)
/* Set the Total CPU and Node count in the system */
val = pci_read_config32(dev, 0x60);
val &= (~0x000F0070);
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
val |= ((total_cpus-1)<<16)|((nodes-1)<<4);
#else
val |= ((nodes-1)<<16)|((nodes-1)<<4);
@@ -1645,7 +1645,7 @@ static void coherent_ht_finalize(unsigned nodes)
(3 << HTTC_HI_PRI_BYP_CNT_SHIFT);
pci_write_config32(dev, HT_TRANSACTION_CONTROL, val);
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
if (rev_a0) {
pci_write_config32(dev, 0x94, 0);
pci_write_config32(dev, 0xb4, 0);
@@ -1665,7 +1665,7 @@ static int apply_cpu_errata_fixes(unsigned nodes)
device_t dev;
uint32_t cmd;
dev = NODE_MC(node);
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
if (is_cpu_pre_c0()) {
/* Errata 66
@@ -1710,7 +1710,7 @@ static int apply_cpu_errata_fixes(unsigned nodes)
#endif
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
/* I can't touch this msr on early buggy cpus, and cannot apply either 169 or 131 */
if (!is_cpu_pre_b3())
#endif
diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c
index fd9fe6063e..4f9d8cafa9 100644
--- a/src/northbridge/amd/amdk8/debug.c
+++ b/src/northbridge/amd/amdk8/debug.c
@@ -57,7 +57,7 @@ static void dump_pci_device(unsigned dev)
print_debug("\n");
}
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index);
static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg)
{
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index f57eb5bf37..ee1945a123 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -67,7 +67,7 @@ static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid
device_t dev;
//actually, only for one HT device HT chain, and unitid is 0
-#if CONFIG_HT_CHAIN_UNITID_BASE == 0
+#if !CONFIG_HT_CHAIN_UNITID_BASE
if(offset_unitid) {
return;
}
@@ -136,8 +136,8 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos)
/* AMD K8 Unsupported 1Ghz? */
if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) {
- #if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1
- #if CONFIG_K8_REV_F_SUPPORT == 0
+ #if CONFIG_K8_HT_FREQ_1G_SUPPORT
+ #if !CONFIG_K8_REV_F_SUPPORT
if (is_cpu_pre_e0()) { // only E0 later support 1GHz
freq_cap &= ~(1 << HT_FREQ_1000Mhz);
}
@@ -149,7 +149,7 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos)
printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\n", pos, freq_cap);
-#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890 == 1
+#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890
freq_cap &= 0x3f;
printk(BIOS_INFO, "Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed.\n");
#endif
@@ -539,7 +539,7 @@ static int optimize_link_read_pointers_chain(uint8_t ht_c_num)
unsigned devn = 1;
#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
- #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+ #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
if(i==0) // to check if it is sb ht chain
#endif
devn = CONFIG_HT_CHAIN_UNITID_BASE;
@@ -671,7 +671,7 @@ static int ht_setup_chains(uint8_t ht_c_num)
#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
- #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+ #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
if(i==0) // to check if it is sb ht chain
#endif
offset_unitid = 1;
diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c
index 7ba2b90406..cc69883007 100644
--- a/src/northbridge/amd/amdk8/misc_control.c
+++ b/src/northbridge/amd/amdk8/misc_control.c
@@ -124,7 +124,7 @@ static void misc_control_init(struct device *dev)
cmd = pci_read_config32(dev, 0x44);
cmd |= (1<<6) | (1<<25);
pci_write_config32(dev, 0x44, cmd );
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
if (is_cpu_pre_c0()) {
/* Errata 58
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index 90b4ebf51d..5eeeda21a4 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -20,7 +20,7 @@
#include <cpu/x86/lapic.h>
#include <cpu/amd/multicore.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <pc80/mc146818rtc.h>
#endif
@@ -256,7 +256,7 @@ static unsigned amdk8_scan_chains(device_t dev, unsigned max)
#endif
offset_unitid = 0;
#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
- #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+ #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
if((nodeid == 0) && (sblink == link->link_num))
#endif
offset_unitid = 1;
@@ -494,7 +494,7 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1
+#if CONFIG_MULTIPLE_VGA_ADAPTERS
extern device_t vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
@@ -635,7 +635,7 @@ static void amdk8_domain_read_resources(device_t dev)
pci_domain_read_resources(dev);
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
/* Initialize the system wide prefetchable memory resources constraints */
resource = new_resource(dev, 2);
resource->limit = 0xfcffffffffULL;
@@ -818,11 +818,11 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id)
}
#endif
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
extern uint64_t uma_memory_base, uma_memory_size;
static void add_uma_resource(struct device *dev, int index)
@@ -840,7 +840,7 @@ static void add_uma_resource(struct device *dev, int index)
static void amdk8_domain_set_resources(device_t dev)
{
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
struct resource *io, *mem1, *mem2;
struct resource *res;
#endif
@@ -857,7 +857,7 @@ static void amdk8_domain_set_resources(device_t dev)
io = find_resource(dev, 0);
io->base = DEVICE_IO_START;
#endif
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
/* Now reallocate the pci resources memory with the
* highest addresses I can manage.
*/
@@ -927,7 +927,7 @@ static void amdk8_domain_set_resources(device_t dev)
* if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole.
* otherwise We reset the hole to the mmio_basek
*/
- #if CONFIG_K8_REV_F_SUPPORT == 0
+ #if !CONFIG_K8_REV_F_SUPPORT
if (!is_cpu_pre_e0()) {
#endif
@@ -947,7 +947,7 @@ static void amdk8_domain_set_resources(device_t dev)
disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
}
- #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
+ #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
//We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
u32 basek_pri;
for (i = 0; i < fx_devs; i++) {
@@ -968,7 +968,7 @@ static void amdk8_domain_set_resources(device_t dev)
#endif
}
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
} // is_cpu_pre_e0
#endif
@@ -997,7 +997,7 @@ static void amdk8_domain_set_resources(device_t dev)
}
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
printk(BIOS_DEBUG, "node %d : uma_memory_base/1024=0x%08llx, mmio_basek=0x%08lx, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk);
if ((uma_memory_base >> 10) < mmio_basek)
printk(BIOS_ALERT, "node %d: UMA memory starts below mmio_basek\n", i);
@@ -1014,10 +1014,10 @@ static void amdk8_domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
#else
high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
@@ -1030,7 +1030,7 @@ static void amdk8_domain_set_resources(device_t dev)
}
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
if(reset_memhole)
- #if CONFIG_K8_REV_F_SUPPORT == 0
+ #if !CONFIG_K8_REV_F_SUPPORT
if(!is_cpu_pre_e0() )
#endif
sizek += hoist_memory(mmio_basek,i);
@@ -1049,7 +1049,7 @@ static void amdk8_domain_set_resources(device_t dev)
/* If sizek == 0, it was split at mmio_basek without a hole.
* Don't create an empty ram_resource.
*/
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
/* Deduct uma memory before reporting because
* this is what the mtrr code expects */
sizek -= uma_memory_size / 1024;
@@ -1057,12 +1057,12 @@ static void amdk8_domain_set_resources(device_t dev)
if (sizek)
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
i, mmio_basek, basek, limitk);
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
#else
high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
@@ -1072,7 +1072,7 @@ static void amdk8_domain_set_resources(device_t dev)
#endif
}
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
add_uma_resource(dev, 7);
#endif
assign_resources(dev->link_list);
@@ -1179,7 +1179,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
sysconf.apicid_offset = bsp_apicid;
disable_siblings = !CONFIG_LOGICAL_CPUS;
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
get_option(&disable_siblings, "multi_core");
#endif
@@ -1248,7 +1248,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
// That is the typical case
if(j == 0 ){
- #if CONFIG_K8_REV_F_SUPPORT == 0
+ #if !CONFIG_K8_REV_F_SUPPORT
e0_later_single_core = is_e0_later_in_bsp(i); // single core
#else
e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index 9cb7c60004..7db338b42a 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -2289,7 +2289,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK;
printk(BIOS_SPEW, "Handling memory hole at 0x%08x (default)\n", hole_startk);
-#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
+#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
/* We need to double check if hole_startk is valid.
* If it is equal to the dram base address in K (base_k),
* we need to decrease it.
@@ -2348,7 +2348,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
{
int i;
u32 whatWait = 0;
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
int suspend = acpi_is_wakeup_early();
#else
int suspend = 0;
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index 33df485c8c..86c409f949 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -2965,7 +2965,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK;
printk_raminit("Handling memory hole at 0x%08x (default)\n", hole_startk);
-#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
+#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
/* We need to double check if the hole_startk is valid, if it is equal
to basek, we need to decrease it some */
uint32_t basek_pri;
@@ -3009,7 +3009,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
}
#endif
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
#include "exit_from_self.c"
#endif
@@ -3017,7 +3017,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
struct sys_info *sysinfo)
{
int i;
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
int suspend = acpi_is_wakeup_early();
#else
int suspend = 0;
@@ -3190,7 +3190,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
}
-#if CONFIG_MEM_TRAIN_SEQ == 0
+#if CONFIG_MEM_TRAIN_SEQ == 0
#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
dqs_timing(controllers, ctrl, tsc0, sysinfo);
#else
diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index 8ddd44fadb..fdec120b50 100644
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -1826,7 +1826,7 @@ static void set_sysinfo_in_ram(unsigned val)
set_htic_bit(0, val, 9);
}
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
#if CONFIG_MEM_TRAIN_SEQ == 0
static int save_index_to_pos(unsigned int dev, int size, int index, int nvram_pos)
@@ -1981,7 +1981,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc
if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out;
printk(BIOS_DEBUG, " done\n");
sysinfo->mem_trained[i]=1;
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
dqs_save_MC_NVRAM((ctrl+i)->f2);
#endif
}
@@ -2103,7 +2103,7 @@ static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sy
memcpy(sysinfo, sysinfox, CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
#endif
set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's
- #if CONFIG_AP_CODE_IN_CAR == 0
+ #if !CONFIG_AP_CODE_IN_CAR
printk(BIOS_DEBUG, "CODE IN ROM AND RUN ON NODE: %02x\n", nodeid);
train_ram(nodeid, sysinfo, sysinfox);
#else
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
index 4af75fd0e2..00b15556ca 100644
--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
@@ -64,14 +64,14 @@ static u16 mctGet_NVbits(u8 index)
//val = 2; /* S4 (Unbuffered SO-DIMMS) */
break;
case NV_BYPMAX:
-#if (CONFIG_GFXUMA == 0)
+#if !CONFIG_GFXUMA
val = 4;
#elif (CONFIG_GFXUMA == 1)
val = 7;
#endif
break;
case NV_RDWRQBYP:
-#if (CONFIG_GFXUMA == 0)
+#if !CONFIG_GFXUMA
val = 2;
#elif (CONFIG_GFXUMA == 1)
val = 3;
@@ -113,7 +113,7 @@ static u16 mctGet_NVbits(u8 index)
//val = 1; /* Enable */
break;
case NV_BurstLen32:
-#if (CONFIG_GFXUMA == 0)
+#if !CONFIG_GFXUMA
val = 0; /* 64 byte mode */
#elif (CONFIG_GFXUMA == 1)
val = 1; /* 32 byte mode */
@@ -132,14 +132,14 @@ static u16 mctGet_NVbits(u8 index)
//val = 1; /* enable */
break;
case NV_BottomIO:
-#if (CONFIG_GFXUMA == 0)
+#if !CONFIG_GFXUMA
val = 0xE0; /* address bits [31:24] */
#elif (CONFIG_GFXUMA == 1)
val = 0xC0; /* address bits [31:24] */
#endif
break;
case NV_BottomUMA:
-#if (CONFIG_GFXUMA == 0)
+#if !CONFIG_GFXUMA
val = 0xE0; /* address bits [31:24] */
#elif (CONFIG_GFXUMA == 1)
val = 0xC0; /* address bits [31:24] */
diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c
index abbc85558c..5c59f7314a 100644
--- a/src/northbridge/amd/gx1/northbridge.c
+++ b/src/northbridge/amd/gx1/northbridge.c
@@ -66,7 +66,7 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = PCI_DEVICE_ID_CYRIX_PCI_MASTER,
};
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -113,7 +113,7 @@ static void pci_domain_set_resources(device_t dev)
tolmk = tomk;
}
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c
index f567766ffc..8da37b4ebf 100644
--- a/src/northbridge/amd/gx2/northbridge.c
+++ b/src/northbridge/amd/gx2/northbridge.c
@@ -273,7 +273,7 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = PCI_DEVICE_ID_NS_GX2,
};
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -294,7 +294,7 @@ static void pci_domain_set_resources(device_t dev)
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tomk - 768); /* Systop - 0xc0000 -> KB */
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c
index 61f3afec5f..9ceceb8740 100644
--- a/src/northbridge/amd/lx/northbridge.c
+++ b/src/northbridge/amd/lx/northbridge.c
@@ -372,7 +372,7 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = PCI_DEVICE_ID_AMD_LXBRIDGE,
};
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -393,7 +393,7 @@ static void pci_domain_set_resources(device_t dev)
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tomk - 768); // Systop - 0xc0000 -> KB
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c
index e6e955fb4f..1fa77d7931 100644
--- a/src/northbridge/intel/e7501/northbridge.c
+++ b/src/northbridge/intel/e7501/northbridge.c
@@ -9,7 +9,7 @@
#include <bitops.h>
#include "chip.h"
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -89,7 +89,7 @@ static void pci_domain_set_resources(device_t dev)
(remaplimitk + 64*1024) - remapbasek);
}
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c
index 6a533cdfb1..9046f43687 100644
--- a/src/northbridge/intel/e7505/northbridge.c
+++ b/src/northbridge/intel/e7505/northbridge.c
@@ -10,7 +10,7 @@
#include "chip.h"
#include "e7505.h"
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -90,7 +90,7 @@ static void pci_domain_set_resources(device_t dev)
(remaplimitk + 64*1024) - remapbasek);
}
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c
index 49c8ba3c71..3b92aa82f9 100644
--- a/src/northbridge/intel/e7520/northbridge.c
+++ b/src/northbridge/intel/e7520/northbridge.c
@@ -16,7 +16,7 @@
static unsigned int max_bus;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -108,7 +108,7 @@ static void pci_domain_set_resources(device_t dev)
(remaplimitk + 64*1024) - remapbasek);
}
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c
index 5e9f9c53e6..ab88899641 100644
--- a/src/northbridge/intel/e7525/northbridge.c
+++ b/src/northbridge/intel/e7525/northbridge.c
@@ -16,7 +16,7 @@
static unsigned int max_bus;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -108,7 +108,7 @@ static void pci_domain_set_resources(device_t dev)
(remaplimitk + 64*1024) - remapbasek);
}
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c
index acd4c3c302..db35b85a6d 100644
--- a/src/northbridge/intel/i3100/northbridge.c
+++ b/src/northbridge/intel/i3100/northbridge.c
@@ -37,7 +37,7 @@
static u32 max_bus;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -129,7 +129,7 @@ static void pci_domain_set_resources(device_t dev)
(remaplimitk + 64*1024) - remapbasek);
}
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 926d5b3afb..050df951e5 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -1197,7 +1197,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
pci_write_config16(ctrl->f0, MCHSCRB, data16);
/* The memory is now setup, use it */
-#if CONFIG_CACHE_AS_RAM == 0
+#if !CONFIG_CACHE_AS_RAM
cache_lbmem(MTRR_TYPE_WRBACK);
#endif
}
diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c
index 136755e1e2..18e57167b4 100644
--- a/src/northbridge/intel/i440bx/northbridge.c
+++ b/src/northbridge/intel/i440bx/northbridge.c
@@ -33,7 +33,7 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = 0x7190,
};
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -72,7 +72,7 @@ static void i440bx_domain_set_resources(device_t dev)
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tolmk - 768);
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/intel/i440lx/northbridge.c b/src/northbridge/intel/i440lx/northbridge.c
index 73be101b09..f34b5abaa8 100644
--- a/src/northbridge/intel/i440lx/northbridge.c
+++ b/src/northbridge/intel/i440lx/northbridge.c
@@ -62,7 +62,7 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = 0x7180,
};
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -101,7 +101,7 @@ static void i440lx_domain_set_resources(device_t dev)
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tolmk - 768);
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c
index 3434c6d71b..78e37285f7 100644
--- a/src/northbridge/intel/i82810/northbridge.c
+++ b/src/northbridge/intel/i82810/northbridge.c
@@ -83,7 +83,7 @@ static int translate_i82810_to_mb[] = {
/* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256,
};
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -147,7 +147,7 @@ static void pci_domain_set_resources(device_t dev)
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tolmk - 768);
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c
index dea05db137..93bdc28196 100644
--- a/src/northbridge/intel/i82830/northbridge.c
+++ b/src/northbridge/intel/i82830/northbridge.c
@@ -64,7 +64,7 @@ int add_northbridge_resources(struct lb_memory *mem)
return 0;
}
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
static void pci_domain_set_resources(device_t dev)
@@ -116,7 +116,7 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(dev->link_list);
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c
index 53f599715b..b59ba50a8b 100644
--- a/src/northbridge/intel/i855/northbridge.c
+++ b/src/northbridge/intel/i855/northbridge.c
@@ -53,7 +53,7 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = 0x3580,
};
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
static void pci_domain_set_resources(device_t dev)
@@ -109,7 +109,7 @@ static void pci_domain_set_resources(device_t dev)
/* ram_resource(dev, idx++, 1024, tolmk - 1024); */
ram_resource(dev, idx++, 768, tolmk - 768);
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index a10bb4a6f1..40b1aaac96 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -93,7 +93,7 @@ static void add_fixed_resources(struct device *dev, int index)
}
}
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -181,7 +181,7 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(dev->link_list);
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index b1f7c72132..b2baaa3d4e 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -143,7 +143,7 @@ static void add_fixed_resources(struct device *dev, int index)
}
}
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -267,7 +267,7 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(dev->link_list);
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c
index 7b7c67b8fc..57245b6bed 100644
--- a/src/northbridge/intel/sch/northbridge.c
+++ b/src/northbridge/intel/sch/northbridge.c
@@ -105,7 +105,7 @@ static void add_fixed_resources(struct device *dev, int index)
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -192,7 +192,7 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(dev->link_list);
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables. */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/rdc/r8610/northbridge.c b/src/northbridge/rdc/r8610/northbridge.c
index 48d830cddf..250ace01ac 100644
--- a/src/northbridge/rdc/r8610/northbridge.c
+++ b/src/northbridge/rdc/r8610/northbridge.c
@@ -32,7 +32,7 @@
#include <smbios.h>
#include "chip.h"
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -69,7 +69,7 @@ static void cpu_pci_domain_set_resources(device_t dev)
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tolmk - 768);
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c
index 2cc331b24d..74e0edff53 100644
--- a/src/northbridge/via/cn400/northbridge.c
+++ b/src/northbridge/via/cn400/northbridge.c
@@ -177,7 +177,7 @@ static void ram_reservation(device_t dev, unsigned long index,
}
#endif
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -207,7 +207,7 @@ static void cn400_domain_set_resources(device_t dev)
tolmk = tomk;
}
-#if CONFIG_WRITE_HIGH_TABLES == 1
+#if CONFIG_WRITE_HIGH_TABLES
/* Locate the High Tables at the Top of Low Memory below the Video RAM */
high_tables_base = ((tolmk - (CONFIG_VIDEO_MB *1024)) * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c
index 6400e223ba..ced4c2f740 100644
--- a/src/northbridge/via/cn700/northbridge.c
+++ b/src/northbridge/via/cn700/northbridge.c
@@ -97,7 +97,7 @@ static const struct pci_driver memctrl_driver __pci_driver = {
.device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL,
};
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -138,7 +138,7 @@ static void pci_domain_set_resources(device_t dev)
tolmk = tomk;
}
-#if CONFIG_WRITE_HIGH_TABLES == 1
+#if CONFIG_WRITE_HIGH_TABLES
high_tables_base = ((tolmk - CONFIG_VIDEO_MB * 1024) * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n",
diff --git a/src/northbridge/via/cx700/northbridge.c b/src/northbridge/via/cx700/northbridge.c
index 9e302983c2..4fca723472 100644
--- a/src/northbridge/via/cx700/northbridge.c
+++ b/src/northbridge/via/cx700/northbridge.c
@@ -32,7 +32,7 @@
#include "chip.h"
#include "northbridge.h"
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -74,7 +74,7 @@ static void pci_domain_set_resources(device_t dev)
tolmk -= 1024; // TOP 1M SM Memory
}
-#if CONFIG_WRITE_HIGH_TABLES == 1
+#if CONFIG_WRITE_HIGH_TABLES
high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n",
diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c
index 3a7ada51fb..92adf3206f 100644
--- a/src/northbridge/via/vt8601/northbridge.c
+++ b/src/northbridge/via/vt8601/northbridge.c
@@ -45,7 +45,7 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = 0x0601, /* 0x8601 is the AGP bridge? */
};
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -89,7 +89,7 @@ static void pci_domain_set_resources(device_t dev)
tolmk = tomk;
}
-#if CONFIG_WRITE_HIGH_TABLES == 1
+#if CONFIG_WRITE_HIGH_TABLES
high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n",
diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c
index 19f14d56a4..5ea2212993 100644
--- a/src/northbridge/via/vt8623/northbridge.c
+++ b/src/northbridge/via/vt8623/northbridge.c
@@ -105,7 +105,7 @@ static const struct pci_driver agp_driver __pci_driver = {
.device = PCI_DEVICE_ID_VIA_8633_1,
};
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -149,7 +149,7 @@ static void pci_domain_set_resources(device_t dev)
tolmk = tomk;
}
-#if CONFIG_WRITE_HIGH_TABLES == 1
+#if CONFIG_WRITE_HIGH_TABLES
high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n",
diff --git a/src/northbridge/via/vx800/examples/chipset_init.c b/src/northbridge/via/vx800/examples/chipset_init.c
index 5e82262d9d..f4798c952d 100644
--- a/src/northbridge/via/vx800/examples/chipset_init.c
+++ b/src/northbridge/via/vx800/examples/chipset_init.c
@@ -18,7 +18,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
#include <arch/acpi.h>
#endif
#include "../vx800.h"
@@ -607,7 +607,7 @@ void init_VIA_chipset(void)
void hardwaremain(int boot_complete)
{
struct lb_memory *lb_mem;
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
void *wake_vec;
#endif