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-rw-r--r--src/soc/amd/common/block/acpimmio/mmio_util.c17
-rw-r--r--src/soc/amd/common/block/include/amdblocks/acpimmio.h7
-rw-r--r--src/soc/amd/common/block/include/amdblocks/acpimmio_map.h19
3 files changed, 31 insertions, 12 deletions
diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c
index 04d5e4af4d..a589ef549a 100644
--- a/src/soc/amd/common/block/acpimmio/mmio_util.c
+++ b/src/soc/amd/common/block/acpimmio/mmio_util.c
@@ -18,13 +18,22 @@
#include <amdblocks/acpimmio_map.h>
#include <amdblocks/acpimmio.h>
-void enable_acpimmio_decode(void)
+void enable_acpimmio_decode_pm24(void)
{
uint32_t dw;
- dw = pm_io_read32(ACPIMMIO_DECODE_REGISTER);
- dw |= ACPIMMIO_DECODE_EN;
- pm_io_write32(ACPIMMIO_DECODE_REGISTER, dw);
+ dw = pm_io_read32(ACPIMMIO_DECODE_REGISTER_24);
+ dw |= PM_24_ACPIMMIO_DECODE_EN;
+ pm_io_write32(ACPIMMIO_DECODE_REGISTER_24, dw);
+}
+
+void enable_acpimmio_decode_pm04(void)
+{
+ uint32_t dw;
+
+ dw = pm_io_read32(ACPIMMIO_DECODE_REGISTER_04);
+ dw |= PM_04_ACPIMMIO_DECODE_EN;
+ pm_io_write32(ACPIMMIO_DECODE_REGISTER_04, dw);
}
/* PM registers are accessed a byte at a time via CD6/CD7 */
diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
index 57d24db5b2..c441ab8f63 100644
--- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h
+++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
@@ -101,7 +101,12 @@
*/
/* Enable the AcpiMmio range at 0xfed80000 */
-void enable_acpimmio_decode(void);
+
+/* For older discrete FCHs */
+void enable_acpimmio_decode_pm24(void);
+
+/* For newer integrated FCHs */
+void enable_acpimmio_decode_pm04(void);
/* Access PM registers using IO cycles */
uint8_t pm_io_read8(uint8_t reg);
diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h
index 755af52d4f..9a1584004b 100644
--- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h
+++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h
@@ -22,16 +22,21 @@
#define PM_INDEX 0xcd6
#define PM_DATA 0xcd7
-/* TODO: In the event this is ported backward far enough, earlier devices
- * enable the decode in PMx24 instead. All discrete FCHs and the Kabini
- * SoC fall into this category. Kabini's successor, Mullins, uses this
- * newer method.
+/* Earlier devices enable the decode in PMx24 instead. All discrete FCHs and
+ * the Kabini SoC fall into this category. Kabini's successor, Mullins, uses
+ * this newer method.
*/
-#define ACPIMMIO_DECODE_REGISTER 0x4
-#define ACPIMMIO_DECODE_EN BIT(0)
+
+#define ACPIMMIO_DECODE_REGISTER_24 0x24
+#define PM_24_ACPIMMIO_DECODE_EN BIT(0)
+
+#define ACPIMMIO_DECODE_REGISTER_04 0x4
+#define PM_04_BIOSRAM_DECODE_EN BIT(0)
+#define PM_04_ACPIMMIO_DECODE_EN BIT(1)
+
/* MMIO register blocks are at fixed offsets from 0xfed80000 and are enabled
- * in PMx24[1] (older implementations) and PMx04[1] (newer implementations).
+ * in PMx24[0] (older implementations) and PMx04[1] (newer implementations).
* PM registers are also accessible via IO CD6/CD7.
*
* All products do not support all blocks below, however AMD has avoided