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-rw-r--r--src/soc/amd/common/block/include/amdblocks/psp.h20
-rw-r--r--src/soc/amd/common/block/psp/Makefile.inc1
-rw-r--r--src/soc/amd/common/block/psp/psp.c86
3 files changed, 4 insertions, 103 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h
index 494f1744f0..42c802d51b 100644
--- a/src/soc/amd/common/block/include/amdblocks/psp.h
+++ b/src/soc/amd/common/block/include/amdblocks/psp.h
@@ -15,24 +15,8 @@
#ifndef __AMD_PSP_H__
#define __AMD_PSP_H__
-#include <amdblocks/agesawrapper.h>
-#include <soc/pci_devs.h>
-#include <types.h>
-
-/* Extra, Special Purpose Registers in the PSP PCI Config Space */
-
-/* PSP Mirror Features Capabilities and Control Register */
-#define PSP_PCI_MIRRORCTRL1_REG 0x44 /* PSP Mirror Ctrl Reg */
-#define PMNXTPTRW_MASK 0xff /* PCI AFCR pointer mask */
-#define PMNXTPTRW_EXPOSE 0xa4 /* Pointer to expose the AFCR */
-
-#define PSP_PCI_EXT_HDR_CTRL 0x48 /* Extra PCI Header Ctrl */
-#define MAGIC_ENABLES 0x34 /* Extra PCI HDR Ctl Enables */
-
-#define PSP_MAILBOX_BASE 0x70 /* Mailbox offset from PCIe BAR */
-
-#define MSR_CU_CBBCFG 0xc00110a2 /* PSP Pvt Blk Base Addr */
-#define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */
+/* Get the mailbox base address - specific to family of device. */
+struct psp_mbox *soc_get_mbox_address(void);
/* x86 to PSP commands */
#define MBOX_BIOS_CMD_DRAM_INFO 0x01
diff --git a/src/soc/amd/common/block/psp/Makefile.inc b/src/soc/amd/common/block/psp/Makefile.inc
index d5f93869c8..2f5de1df9c 100644
--- a/src/soc/amd/common/block/psp/Makefile.inc
+++ b/src/soc/amd/common/block/psp/Makefile.inc
@@ -1,3 +1,4 @@
bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c
romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c
ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c
+smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c
diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c
index 9c053c2c39..7ec8d7b0c9 100644
--- a/src/soc/amd/common/block/psp/psp.c
+++ b/src/soc/amd/common/block/psp/psp.c
@@ -33,73 +33,6 @@ static const char *psp_status_init_timeout = "error: PSP init timeout";
static const char *psp_status_cmd_timeout = "error: PSP command timeout";
static const char *psp_status_noerror = "";
-static void psp_bar_init_early(void)
-{
- u32 psp_mmio_size;
- u32 value32;
- u32 base, limit;
-
- /* Check for presence of the PSP */
- if (pci_read_config32(SOC_PSP_DEV, PCI_VENDOR_ID) == 0xffffffff) {
- printk(BIOS_WARNING, "PSP: SOC_PSP_DEV device not found at D%xF%x\n",
- PSP_DEV, PSP_FUNC);
- return;
- }
-
- /* Check if PSP BAR has been assigned, and if so, just return */
- if (pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4) &
- ~PCI_BASE_ADDRESS_MEM_ATTR_MASK)
- return;
-
- /* Otherwise, do an early init of the BAR */
- pci_write_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4, 0xffffffff);
- psp_mmio_size = ~pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4) + 1;
- printk(BIOS_SPEW, "PSP: BAR size is 0x%x\n", psp_mmio_size);
- /* Assign BAR to an initial temporarily defined region */
- pci_write_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4,
- PSP_MAILBOX_BAR3_BASE);
-
- /* Route MMIO through the northbridge */
- pci_write_config32(SOC_PSP_DEV, PCI_COMMAND,
- (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
- limit = ((PSP_MAILBOX_BAR3_BASE + psp_mmio_size - 1) >> 8) & ~0xff;
- pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(7), limit);
- base = (PSP_MAILBOX_BAR3_BASE >> 8) | MMIO_WE | MMIO_RE;
- pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(7), base);
- pci_write_config32(SOC_PSP_DEV, PSP_PCI_EXT_HDR_CTRL, MAGIC_ENABLES);
-
- /* Update the capability chain */
- value32 = pci_read_config32(SOC_PSP_DEV, PSP_PCI_MIRRORCTRL1_REG);
- value32 &= ~PMNXTPTRW_MASK;
- value32 |= PMNXTPTRW_EXPOSE;
- pci_write_config32(SOC_PSP_DEV, PSP_PCI_MIRRORCTRL1_REG, value32);
-}
-
-static uintptr_t get_psp_bar3_addr(void)
-{
- uintptr_t psp_mmio;
-
- /* Check for presence of the PSP */
- if (pci_read_config32(SOC_PSP_DEV, PCI_VENDOR_ID) == 0xffffffff) {
- printk(BIOS_WARNING, "PSP: No SOC_PSP_DEV found at D%xF%x\n",
- PSP_DEV, PSP_FUNC);
- return 0;
- }
-
- /* D8F0x48[12] is the Bar3Hide flag, check it */
- if (pci_read_config32(SOC_PSP_DEV, PSP_PCI_EXT_HDR_CTRL) & BAR3HIDE) {
- psp_mmio = rdmsr(MSR_CU_CBBCFG).lo;
- if (psp_mmio == 0xffffffff) {
- printk(BIOS_WARNING, "PSP: BAR hidden, MSR val uninitialized\n");
- return 0;
- }
- return psp_mmio;
- } else {
- return pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4) &
- ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
- }
-}
-
static const char *status_to_string(int err)
{
switch (err) {
@@ -120,23 +53,6 @@ static const char *status_to_string(int err)
}
}
-static struct psp_mbox *get_mbox_address(void)
-{
- uintptr_t baseptr;
-
- baseptr = get_psp_bar3_addr();
- if (baseptr == 0) {
- psp_bar_init_early();
- baseptr = get_psp_bar3_addr();
- if (baseptr == 0) {
- printk(BIOS_WARNING, "PSP: %s(), psp_bar_init_early() failed...\n",
- __func__);
- return NULL;
- }
- }
- return (struct psp_mbox *)(baseptr + PSP_MAILBOX_BASE);
-}
-
static u32 rd_mbox_sts(struct psp_mbox *mbox)
{
return read32(&mbox->mbox_status);
@@ -192,7 +108,7 @@ static int wait_command(struct psp_mbox *mbox)
static int send_psp_command(u32 command, void *buffer)
{
- struct psp_mbox *mbox = get_mbox_address();
+ struct psp_mbox *mbox = soc_get_mbox_address();
if (!mbox)
return -PSPSTS_NOBASE;