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-rw-r--r--src/soc/amd/picasso/acpi/acpi_wake_source.asl32
-rw-r--r--src/soc/amd/picasso/acpi/cpu.asl49
-rw-r--r--src/soc/amd/picasso/acpi/globalnvs.asl77
-rw-r--r--src/soc/amd/picasso/acpi/northbridge.asl134
-rw-r--r--src/soc/amd/picasso/acpi/pci_int.asl469
-rw-r--r--src/soc/amd/picasso/acpi/pcie.asl99
-rw-r--r--src/soc/amd/picasso/acpi/sb_fch.asl153
-rw-r--r--src/soc/amd/picasso/acpi/sb_pci0_fch.asl619
-rw-r--r--src/soc/amd/picasso/acpi/sleepstates.asl39
-rw-r--r--src/soc/amd/picasso/acpi/soc.asl31
-rw-r--r--src/soc/amd/picasso/acpi/usb.asl392
11 files changed, 2094 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/acpi/acpi_wake_source.asl b/src/soc/amd/picasso/acpi/acpi_wake_source.asl
new file mode 100644
index 0000000000..fa01802618
--- /dev/null
+++ b/src/soc/amd/picasso/acpi/acpi_wake_source.asl
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB)
+{
+ Method (_SWS)
+ {
+ /* Index into PM1 for device that caused wake */
+ Return (\PM1I)
+ }
+}
+
+Scope (\_GPE)
+{
+ Method (_SWS)
+ {
+ /* Index into GPE for device that caused wake */
+ Return (\GPEI)
+ }
+}
diff --git a/src/soc/amd/picasso/acpi/cpu.asl b/src/soc/amd/picasso/acpi/cpu.asl
new file mode 100644
index 0000000000..414326ecf1
--- /dev/null
+++ b/src/soc/amd/picasso/acpi/cpu.asl
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Required function by EC, Notify OS to re-read CPU tables */
+Method (PNOT)
+{
+}
+
+/*
+ * Processor Object
+ */
+/* These devices are created at runtime */
+External (\_PR.P000, DeviceObj)
+External (\_PR.P001, DeviceObj)
+External (\_PR.P002, DeviceObj)
+External (\_PR.P003, DeviceObj)
+External (\_PR.P004, DeviceObj)
+External (\_PR.P005, DeviceObj)
+External (\_PR.P006, DeviceObj)
+External (\_PR.P007, DeviceObj)
+
+/* Return a package containing enabled processor entries */
+Method (PPKG)
+{
+ If (LGreaterEqual (\PCNT, 2)) {
+ Return (Package ()
+ {
+ \_PR.P000,
+ \_PR.P001
+ })
+ } Else {
+ Return (Package ()
+ {
+ \_PR.P000
+ })
+ }
+}
diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl
new file mode 100644
index 0000000000..03d205f8d3
--- /dev/null
+++ b/src/soc/amd/picasso/acpi/globalnvs.asl
@@ -0,0 +1,77 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * NOTE: The layout of the GNVS structure below must match the layout in
+ * soc/amd/stoneyridge/include/soc/nvs.h !!!
+ *
+ */
+
+External (NVSA)
+
+OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
+Field (GNVS, ByteAcc, NoLock, Preserve)
+{
+ /* Miscellaneous */
+ Offset (0x00),
+ PCNT, 8, // 0x00 - Processor Count
+ PPCM, 8, // 0x01 - Max PPC State
+ LIDS, 8, // 0x02 - LID State
+ PWRS, 8, // 0x03 - AC Power State
+ DPTE, 8, // 0x04 - Enable DPTF
+ CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console
+ PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index
+ GPEI, 64, // 0x11 - 0x18 - GPE Wake Source
+ NHLA, 64, // 0x19 - 0x20 - NHLT Address
+ NHLL, 32, // 0x21 - 0x24 - NHLT Length
+ PRT0, 32, // 0x25 - 0x28 - PERST_0 Address
+ SCDP, 8, // 0x29 - SD_CD GPIO portid
+ SCDO, 8, // 0x2A - GPIO pad offset relative to the community
+ TMPS, 8, // 0x2B - Temperature Sensor ID
+ TLVL, 8, // 0x2C - Throttle Level Limit
+ FLVL, 8, // 0x2D - Current FAN Level
+ TCRT, 8, // 0x2E - Critical Threshold
+ TPSV, 8, // 0x2F - Passive Threshold
+ TMAX, 8, // 0x30 - CPU Tj_max
+ Offset (0x34), // 0x34 - AOAC Device Enables
+ , 5,
+ IC0E, 1, // I2C0, 5
+ IC1E, 1, // I2C1, 6
+ IC2E, 1, // I2C2, 7
+ IC3E, 1, // I2C3, 8
+ , 2,
+ UT0E, 1, // UART0, 11
+ UT1E, 1, // UART1, 12
+ , 2,
+ ST_E, 1, // SATA, 15
+ , 2,
+ EHCE, 1, // EHCI, 18
+ , 4,
+ XHCE, 1, // XCHI, 23
+ SD_E, 1, // SD, 24
+ , 2,
+ ESPI, 1, // ESPI, 27
+ , 4,
+ FW00, 16, // 0x38 - xHCI FW ROM addr, boot RAM
+ FW02, 16, // 0x3A - xHCI FW ROM addr, Instruction RAM
+ FW01, 32, // 0x3C - xHCI FW RAM addr, boot RAM
+ FW03, 32, // 0x40 - xHCI FW RAM addr, Instruction RAM
+ EH10, 32, // 0x44 - EHCI BAR
+ /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
+ Offset (0x100),
+ #include <vendorcode/google/chromeos/acpi/gnvs.asl>
+}
diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl
new file mode 100644
index 0000000000..fe78534403
--- /dev/null
+++ b/src/soc/amd/picasso/acpi/northbridge.asl
@@ -0,0 +1,134 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ * Copyright (C) 2016 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Note: Only need HID on Primary Bus */
+External (TOM1)
+External (TOM2)
+Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */
+Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
+Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
+
+/* Describe the Northbridge devices */
+
+Method(_BBN, 0, NotSerialized) /* Bus number = 0 */
+{
+ Return(Zero)
+}
+
+Method(_STA, 0, NotSerialized)
+{
+ Return(0x0B) /* Status is visible */
+}
+
+Method(_PRT,0, NotSerialized)
+{
+ If(PMOD)
+ {
+ Return(APR0) /* APIC mode */
+ }
+ Return (PR0) /* PIC Mode */
+}
+
+Device(AMRT) {
+ Name(_ADR, 0x00000000)
+} /* end AMRT */
+
+/* Internal Graphics */
+Device(IGFX) {
+ Name(_ADR, 0x00010000)
+}
+
+/* Gpp 0 */
+Device(PBR4) {
+ Name(_ADR, 0x00020001)
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS4) } /* APIC mode */
+ Return (PS4) /* PIC Mode */
+ } /* end _PRT */
+} /* end PBR4 */
+
+/* Gpp 1 */
+Device(PBR5) {
+ Name(_ADR, 0x00020002)
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS5) } /* APIC mode */
+ Return (PS5) /* PIC Mode */
+ } /* end _PRT */
+} /* end PBR5 */
+
+/* Gpp 2 */
+Device(PBR6) {
+ Name(_ADR, 0x00020003)
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS6) } /* APIC mode */
+ Return (PS6) /* PIC Mode */
+ } /* end _PRT */
+} /* end PBR6 */
+
+/* Gpp 3 */
+Device(PBR7) {
+ Name(_ADR, 0x00020004)
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS7) } /* APIC mode */
+ Return (PS7) /* PIC Mode */
+ } /* end _PRT */
+} /* end PBR7 */
+
+/* Gpp 4 */
+Device(PBR8) {
+ Name(_ADR, 0x00020005)
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS8) } /* APIC mode */
+ Return (PS8) /* PIC Mode */
+ } /* end _PRT */
+} /* end PBR8 */
+
+Device(AZHD) { /* 0:9.2 - HD Audio */
+ Name(_ADR, 0x00090002)
+ OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+ Field(AZPD, AnyAcc, NoLock, Preserve) {
+ offset (0x42),
+ NSDI, 1,
+ NSDO, 1,
+ NSEN, 1,
+ offset (0x44),
+ IPCR, 4,
+ offset (0x54),
+ PWST, 2,
+ , 6,
+ PMEB, 1,
+ , 6,
+ PMST, 1,
+ offset (0x62),
+ MMCR, 1,
+ offset (0x64),
+ MMLA, 32,
+ offset (0x68),
+ MMHA, 32,
+ offset (0x6c),
+ MMDT, 16,
+ }
+
+ Method (_INI, 0, NotSerialized)
+ {
+ If (LEqual (OSVR, 0x03))
+ {
+ Store (Zero, NSEN)
+ Store (One, NSDO)
+ Store (One, NSDI)
+ }
+ }
+} /* end AZHD */
diff --git a/src/soc/amd/picasso/acpi/pci_int.asl b/src/soc/amd/picasso/acpi/pci_int.asl
new file mode 100644
index 0000000000..617b9eb86c
--- /dev/null
+++ b/src/soc/amd/picasso/acpi/pci_int.asl
@@ -0,0 +1,469 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+ /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
+ OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */
+ Field(PCFG, ByteAcc, NoLock, Preserve) {
+ /* Byte offsets are computed using the following technique:
+ * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
+ * The 8 comes from 8 functions per device, and 4096 bytes per function config space
+ */
+ Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
+ STB5, 32,
+ Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
+ PT0D, 1,
+ PT1D, 1,
+ PT2D, 1,
+ PT3D, 1,
+ PT4D, 1,
+ PT5D, 1,
+ PT6D, 1,
+ PT7D, 1,
+ PT8D, 1,
+ PT9D, 1,
+ Offset(0x000a0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
+ SBIE, 1,
+ SBME, 1,
+ Offset(0x000a0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
+ SBRI, 8,
+ Offset(0x000a0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
+ SBB1, 32,
+ Offset(0x000a0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
+ ,14,
+ P92E, 1, /* Port92 decode enable */
+ }
+
+ OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+ Field(SB5, AnyAcc, NoLock, Preserve){
+ /* Port 0 */
+ Offset(0x120), /* Port 0 Task file status */
+ P0ER, 1,
+ , 2,
+ P0DQ, 1,
+ , 3,
+ P0BY, 1,
+ Offset(0x128), /* Port 0 Serial ATA status */
+ P0DD, 4,
+ , 4,
+ P0IS, 4,
+ Offset(0x12c), /* Port 0 Serial ATA control */
+ P0DI, 4,
+ Offset(0x130), /* Port 0 Serial ATA error */
+ , 16,
+ P0PR, 1,
+
+ /* Port 1 */
+ offset(0x1a0), /* Port 1 Task file status */
+ P1ER, 1,
+ , 2,
+ P1DQ, 1,
+ , 3,
+ P1BY, 1,
+ Offset(0x1a8), /* Port 1 Serial ATA status */
+ P1DD, 4,
+ , 4,
+ P1IS, 4,
+ Offset(0x1ac), /* Port 1 Serial ATA control */
+ P1DI, 4,
+ Offset(0x1b0), /* Port 1 Serial ATA error */
+ , 16,
+ P1PR, 1,
+
+ /* Port 2 */
+ Offset(0x220), /* Port 2 Task file status */
+ P2ER, 1,
+ , 2,
+ P2DQ, 1,
+ , 3,
+ P2BY, 1,
+ Offset(0x228), /* Port 2 Serial ATA status */
+ P2DD, 4,
+ , 4,
+ P2IS, 4,
+ Offset(0x22c), /* Port 2 Serial ATA control */
+ P2DI, 4,
+ Offset(0x230), /* Port 2 Serial ATA error */
+ , 16,
+ P2PR, 1,
+
+ /* Port 3 */
+ Offset(0x2a0), /* Port 3 Task file status */
+ P3ER, 1,
+ , 2,
+ P3DQ, 1,
+ , 3,
+ P3BY, 1,
+ Offset(0x2a8), /* Port 3 Serial ATA status */
+ P3DD, 4,
+ , 4,
+ P3IS, 4,
+ Offset(0x2aC), /* Port 3 Serial ATA control */
+ P3DI, 4,
+ Offset(0x2b0), /* Port 3 Serial ATA error */
+ , 16,
+ P3PR, 1,
+ }
+
+ Method(_PIC, 0x01, NotSerialized)
+ {
+ If (Arg0)
+ {
+ \_SB.CIRQ()
+ }
+ Store(Arg0, PMOD)
+ }
+
+ Method(CIRQ, 0x00, NotSerialized){
+ }
+
+ Name(IRQB, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Shared){15}
+ })
+
+ Name(IRQP, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
+ })
+
+ Name(PITF, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Exclusive){9}
+ })
+
+ Device(INTA) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 1)
+
+ Method(_STA, 0) {
+ if (PIRA) {
+ Return(0x0b) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTA._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_DIS\n") */
+ } /* End Method(_SB.INTA._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTA._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRA, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTA._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKA\\_SRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIRA)
+ } /* End Method(_SB.INTA._SRS) */
+ } /* End Device(INTA) */
+
+ Device(INTB) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 2)
+
+ Method(_STA, 0) {
+ if (PIRB) {
+ Return(0x0b) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTB._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_DIS\n") */
+ } /* End Method(_SB.INTB._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTB._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRB, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTB._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKB\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIRB)
+ } /* End Method(_SB.INTB._SRS) */
+ } /* End Device(INTB) */
+
+ Device(INTC) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 3)
+
+ Method(_STA, 0) {
+ if (PIRC) {
+ Return(0x0b) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTC._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_DIS\n") */
+ } /* End Method(_SB.INTC._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTC._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRC, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTC._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKC\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIRC)
+ } /* End Method(_SB.INTC._SRS) */
+ } /* End Device(INTC) */
+
+ Device(INTD) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 4)
+
+ Method(_STA, 0) {
+ if (PIRD) {
+ Return(0x0b) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTD._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_DIS\n") */
+ } /* End Method(_SB.INTD._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTD._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRD, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTD._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKD\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIRD)
+ } /* End Method(_SB.INTD._SRS) */
+ } /* End Device(INTD) */
+
+ Device(INTE) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 5)
+
+ Method(_STA, 0) {
+ if (PIRE) {
+ Return(0x0b) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTE._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_DIS\n") */
+ } /* End Method(_SB.INTE._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTE._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRE, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTE._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKE\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIRE)
+ } /* End Method(_SB.INTE._SRS) */
+ } /* End Device(INTE) */
+
+ Device(INTF) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 6)
+
+ Method(_STA, 0) {
+ if (PIRF) {
+ Return(0x0b) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTF._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_DIS\n") */
+ } /* End Method(_SB.INTF._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_PRS\n") */
+ Return(PITF)
+ } /* Method(_SB.INTF._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRF, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTF._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKF\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIRF)
+ } /* End Method(_SB.INTF._SRS) */
+ } /* End Device(INTF) */
+
+ Device(INTG) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 7)
+
+ Method(_STA, 0) {
+ if (PIRG) {
+ Return(0x0b) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTG._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_DIS\n") */
+ } /* End Method(_SB.INTG._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTG._CRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRG, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTG._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKG\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIRG)
+ } /* End Method(_SB.INTG._SRS) */
+ } /* End Device(INTG) */
+
+ Device(INTH) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 8)
+
+ Method(_STA, 0) {
+ if (PIRH) {
+ Return(0x0b) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTH._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_DIS\n") */
+ } /* End Method(_SB.INTH._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTH._CRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRH, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTH._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKH\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIRH)
+ } /* End Method(_SB.INTH._SRS) */
+ } /* End Device(INTH) */
diff --git a/src/soc/amd/picasso/acpi/pcie.asl b/src/soc/amd/picasso/acpi/pcie.asl
new file mode 100644
index 0000000000..925187209c
--- /dev/null
+++ b/src/soc/amd/picasso/acpi/pcie.asl
@@ -0,0 +1,99 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+ /* PCI IRQ mapping registers, C00h-C01h. */
+ OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002)
+ Field(PRQM, ByteAcc, NoLock, Preserve) {
+ PRQI, 0x00000008,
+ PRQD, 0x00000008, /* Offset: 1h */
+ }
+ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+ PIRA, 0x00000008, /* Index 0 */
+ PIRB, 0x00000008, /* Index 1 */
+ PIRC, 0x00000008, /* Index 2 */
+ PIRD, 0x00000008, /* Index 3 */
+ PIRE, 0x00000008, /* Index 4 */
+ PIRF, 0x00000008, /* Index 5 */
+ PIRG, 0x00000008, /* Index 6 */
+ PIRH, 0x00000008, /* Index 7 */
+ }
+
+ /* PCI Error control register */
+ OperationRegion(PERC, SystemIO, 0x00000c14, 0x00000001)
+ Field(PERC, ByteAcc, NoLock, Preserve) {
+ SENS, 0x00000001,
+ PENS, 0x00000001,
+ SENE, 0x00000001,
+ PENE, 0x00000001,
+ }
+
+ /* Client Management index/data registers */
+ OperationRegion(CMT, SystemIO, 0x00000c50, 0x00000002)
+ Field(CMT, ByteAcc, NoLock, Preserve) {
+ CMTI, 8,
+ /* Client Management Data register */
+ G64E, 1,
+ G64O, 1,
+ G32O, 2,
+ , 2,
+ GPSL, 2,
+ }
+
+ /* GPM Port register */
+ OperationRegion(GPT, SystemIO, 0x00000c52, 0x00000001)
+ Field(GPT, ByteAcc, NoLock, Preserve) {
+ GPB0,1,
+ GPB1,1,
+ GPB2,1,
+ GPB3,1,
+ GPB4,1,
+ GPB5,1,
+ GPB6,1,
+ GPB7,1,
+ }
+
+ /* Flash ROM program enable register */
+ OperationRegion(FRE, SystemIO, 0x00000c6F, 0x00000001)
+ Field(FRE, ByteAcc, NoLock, Preserve) {
+ , 0x00000006,
+ FLRE, 0x00000001,
+ }
+
+ /* PM2 index/data registers */
+ OperationRegion(PM2R, SystemIO, 0x00000Cd0, 0x00000002)
+ Field(PM2R, ByteAcc, NoLock, Preserve) {
+ PM2I, 0x00000008,
+ PM2D, 0x00000008,
+ }
+
+ /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */
+ OperationRegion(PIOR, SystemIO, 0x00000Cd6, 0x00000002)
+ Field(PIOR, ByteAcc, NoLock, Preserve) {
+ PIOI, 0x00000008,
+ PIOD, 0x00000008,
+ }
+
+ IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
+ Offset(0x60), /* AcpiPm1EvgBlk */
+ P1EB, 16,
+ Offset(0xee),
+ UPWS, 3,
+ }
+ OperationRegion (P1E0, SystemIO, P1EB, 0x04)
+ Field (P1E0, ByteAcc, Nolock, Preserve) {
+ Offset(0x02),
+ , 14,
+ PEWD, 1,
+ }
diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl
new file mode 100644
index 0000000000..e7975f8d94
--- /dev/null
+++ b/src/soc/amd/picasso/acpi/sb_fch.asl
@@ -0,0 +1,153 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+
+Device (AAHB)
+{
+ Name (_HID, "AAHB0000")
+ Name (_UID, 0x0)
+ Name (_CRS, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000)
+ })
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+}
+
+Device (GPIO)
+{
+ Name (_HID, GPIO_DEVICE_NAME)
+ Name (_CID, GPIO_DEVICE_NAME)
+ Name (_UID, 0)
+ Name (_DDN, GPIO_DEVICE_DESC)
+
+ Name (_CRS, ResourceTemplate()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
+ { 7 }
+ Memory32Fixed (ReadWrite, 0xFED81500, 0x300)
+ })
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+}
+
+Device (FUR0)
+{
+ Name (_HID, "AMD0020")
+ Name (_UID, 0x0)
+ Name (_CRS, ResourceTemplate()
+ {
+ IRQ (Edge, ActiveHigh, Exclusive) { 10 }
+ Memory32Fixed (ReadWrite, 0xFEDC6000, 0x2000)
+ })
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+}
+
+Device (FUR1) {
+ Name (_HID, "AMD0020")
+ Name (_UID, 0x1)
+ Name (_CRS, ResourceTemplate()
+ {
+ IRQ (Edge, ActiveHigh, Exclusive) { 11 }
+ Memory32Fixed (ReadWrite, 0xFEDC8000, 0x2000)
+ })
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+}
+
+Device (I2CA) {
+ Name (_HID, "AMD0010")
+ Name (_UID, 0x0)
+ Name (_CRS, ResourceTemplate()
+ {
+ IRQ (Edge, ActiveHigh, Exclusive) { 3 }
+ Memory32Fixed (ReadWrite, 0xFEDC2000, 0x1000)
+ })
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+}
+
+Device (I2CB)
+{
+ Name (_HID, "AMD0010")
+ Name (_UID, 0x1)
+ Name (_CRS, ResourceTemplate()
+ {
+ IRQ (Edge, ActiveHigh, Exclusive) { 15 }
+ Memory32Fixed (ReadWrite, 0xFEDC3000, 0x1000)
+ })
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+}
+
+Device (I2CC) {
+ Name (_HID, "AMD0010")
+ Name (_UID, 0x2)
+ Name (_CRS, ResourceTemplate()
+ {
+ IRQ (Edge, ActiveHigh, Exclusive) { 6 }
+ Memory32Fixed (ReadWrite, 0xFEDC4000, 0x1000)
+ })
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+}
+
+Device (I2CD)
+{
+ Name (_HID, "AMD0010")
+ Name (_UID, 0x3)
+ Name (_CRS, ResourceTemplate() {
+ IRQ (Edge, ActiveHigh, Exclusive) { 14 }
+ Memory32Fixed(ReadWrite, 0xFEDC5000, 0x1000)
+ })
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+}
+
+Device (MISC)
+{
+ Name (_HID, "AMD0040")
+ Name (_UID, 0x3)
+ Name (_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100)
+ })
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+}
diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
new file mode 100644
index 0000000000..3623814080
--- /dev/null
+++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
@@ -0,0 +1,619 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+External(\_SB.ALIB, MethodObj)
+
+/* System Bus */
+/* _SB.PCI0 */
+
+/* Operating System Capabilities Method */
+Method(_OSC,4)
+{
+ /* Check for proper PCI/PCIe UUID */
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
+ {
+ /* Let OS control everything */
+ Return (Arg3)
+ } Else {
+ CreateDWordField(Arg3,0,CDW1)
+ Or(CDW1,4,CDW1) // Unrecognized UUID
+ Return(Arg3)
+ }
+}
+
+/* Describe the Southbridge devices */
+
+/* 0:11.0 - SATA */
+Device(STCR) {
+ Name(_ADR, 0x00110000)
+} /* end STCR */
+
+/* 0:14.0 - SMBUS */
+Device(SBUS) {
+ Name(_ADR, 0x00140000)
+} /* end SBUS */
+
+#include "usb.asl"
+
+/* 0:14.2 - I2S Audio */
+
+/* 0:14.3 - LPC */
+#include <soc/amd/common/acpi/lpc.asl>
+
+/* 0:14.7 - SD Controller */
+Device(SDCN) {
+ Name(_ADR, 0x00140007)
+
+ Method(_PS0) {
+ FDDC(24, 0)
+ }
+ Method(_PS3) {
+ FDDC(24, 3)
+ }
+ Method(_PSC) {
+ Return(SDTD)
+ }
+} /* end SDCN */
+
+Name(CRES, ResourceTemplate() {
+ /* Set the Bus number and Secondary Bus number for the PCI0 device
+ * The Secondary bus range for PCI0 lets the system
+ * know what bus values are allowed on the downstream
+ * side of this PCI bus if there is a PCI-PCI bridge.
+ * PCI busses can have 256 secondary busses which
+ * range from [0-0xFF] but they do not need to be
+ * sequential.
+ */
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, /* address granularity */
+ 0x0000, /* range minimum */
+ 0x00ff, /* range maximum */
+ 0x0000, /* translation */
+ 0x0100, /* length */
+ ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */
+
+ IO(Decode16, 0x0cf8, 0x0cf8, 1, 8)
+
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x0000, /* range minimum */
+ 0x0cf7, /* range maximum */
+ 0x0000, /* translation */
+ 0x0cf8 /* length */
+ )
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x03b0, /* range minimum */
+ 0x03df, /* range maximum */
+ 0x0000, /* translation */
+ 0x0030 /* length */
+ )
+
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x0d00, /* range minimum */
+ 0xffff, /* range maximum */
+ 0x0000, /* translation */
+ 0xf300 /* length */
+ )
+
+ Memory32Fixed(READONLY, 0x000a0000, 0x00020000, VGAM) /* VGA memory space */
+ Memory32Fixed(READONLY, 0x000c0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
+
+ /* memory space for PCI BARs below 4GB */
+ Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
+}) /* End Name(_SB.PCI0.CRES) */
+
+Method(_CRS, 0) {
+ /* DBGO("\\_SB\\PCI0\\_CRS\n") */
+ CreateDWordField(CRES, ^MMIO._BAS, MM1B)
+ CreateDWordField(CRES, ^MMIO._LEN, MM1L)
+
+ /*
+ * Declare memory between TOM1 and 4GB as available
+ * for PCI MMIO.
+ * Use ShiftLeft to avoid 64bit constant (for XP).
+ * This will work even if the OS does 32bit arithmetic, as
+ * 32bit (0x00000000 - TOM1) will wrap and give the same
+ * result as 64bit (0x100000000 - TOM1).
+ */
+ Store(TOM1, MM1B)
+ ShiftLeft(0x10000000, 4, Local0)
+ Subtract(Local0, TOM1, Local0)
+ Store(Local0, MM1L)
+
+ Return(CRES) /* note to change the Name buffer */
+} /* end of Method(_SB.PCI0._CRS) */
+
+/*
+ *
+ * FIRST METHOD CALLED UPON BOOT
+ *
+ * 1. If debugging, print current OS and ACPI interpreter.
+ * 2. Get PCI Interrupt routing from ACPI VSM, this
+ * value is based on user choice in BIOS setup.
+ */
+Method(_INI, 0, Serialized) {
+ /* DBGO("\\_SB\\_INI\n") */
+ /* DBGO(" DSDT.ASL code from ") */
+ /* DBGO(__DATE__) */
+ /* DBGO(" ") */
+ /* DBGO(__TIME__) */
+ /* DBGO("\n Sleep states supported: ") */
+ /* DBGO("\n") */
+ /* DBGO(" \\_OS=") */
+ /* DBGO(\_OS) */
+ /* DBGO("\n \\_REV=") */
+ /* DBGO(\_REV) */
+ /* DBGO("\n") */
+
+ /* Determine the OS we're running on */
+ OSFL()
+
+ /* Send ALIB Function 1 the AC/DC state */
+ Name(F1BF, Buffer(0x03){})
+ CreateWordField(F1BF, 0, F1SZ)
+ CreateByteField(F1BF, 2, F1DA)
+
+ Store(3, F1SZ)
+ Store(\PWRS, F1DA)
+
+ \_SB.ALIB(1, F1BF)
+
+} /* End Method(_SB._INI) */
+
+Method(OSFL, 0){
+
+ if (LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
+
+ if (CondRefOf(\_OSI))
+ {
+ Store(1, OSVR) /* Assume some form of XP */
+ if (\_OSI("Windows 2006")) /* Vista */
+ {
+ Store(2, OSVR)
+ }
+ } else {
+ If(WCMP(\_OS,"Linux")) {
+ Store(3, OSVR) /* Linux */
+ } Else {
+ Store(4, OSVR) /* Gotta be WinCE */
+ }
+ }
+ Return(OSVR)
+}
+
+OperationRegion(SMIC, SystemMemory, 0xfed80000, 0x80000)
+Field( SMIC, ByteAcc, NoLock, Preserve) {
+ /* MISC registers */
+ offset (0x03ee),
+ U3PS, 2, /* Usb3PowerSel */
+
+ offset (0x0e28),
+ ,29 ,
+ SARP, 1, /* Sata Ref Clock Powerdown */
+ U2RP, 1, /* Usb2 Ref Clock Powerdown */
+ U3RP, 1, /* Usb3 Ref Clock Powerdown */
+
+ /* XHCI_PM registers */
+ offset (0x1c00),
+ , 1,
+ ,6,
+ U3PY, 1,
+ , 7,
+ UD3P, 1, /* bit 15 */
+ U3PR, 1, /* bit 16 */
+ , 11,
+ FWLM, 1, /* FirmWare Load Mode */
+ FPLS, 1, /* Fw PreLoad Start */
+ FPLC, 1, /* Fw PreLoad Complete */
+
+ offset (0x1c04),
+ UA04, 16,
+ , 15,
+ ROAM, 1, /* 1= ROM 0=RAM */
+
+ offset (0x1c08),
+ UA08, 32,
+
+ /* AOAC Registers */
+ offset (0x1e4a), /* I2C0 D3 Control */
+ I0TD, 2,
+ , 1,
+ I0PD, 1,
+ offset (0x1e4b), /* I2C0 D3 State */
+ I0DS, 3,
+
+ offset (0x1e4c), /* I2C1 D3 Control */
+ I1TD, 2,
+ , 1,
+ I1PD, 1,
+ offset (0x1e4d), /* I2C1 D3 State */
+ I1DS, 3,
+
+ offset (0x1e4e), /* I2C2 D3 Control */
+ I2TD, 2,
+ , 1,
+ I2PD, 1,
+ offset (0x1e4f), /* I2C2 D3 State */
+ I2DS, 3,
+
+ offset (0x1e50), /* I2C3 D3 Control */
+ I3TD, 2,
+ , 1,
+ I3PD, 1,
+ offset (0x1e51), /* I2C3 D3 State */
+ I3DS, 3,
+
+ offset (0x1e56), /* UART0 D3 Control */
+ U0TD, 2,
+ , 1,
+ U0PD, 1,
+ offset (0x1e57), /* UART0 D3 State */
+ U0DS, 3,
+
+ offset (0x1e58), /* UART1 D3 Control */
+ U1TD, 2,
+ , 1,
+ U1PD, 1,
+ offset (0x1e59), /* UART1 D3 State */
+ U1DS, 3,
+
+ offset (0x1e5e), /* SATA D3 Control */
+ SATD, 2,
+ , 1,
+ SAPD, 1,
+ offset (0x1e5f), /* SATA D3 State */
+ SADS, 3,
+
+ offset (0x1e64), /* USB2 D3 Control */
+ U2TD, 2,
+ , 1,
+ U2PD, 1,
+ offset (0x1e65), /* USB2 D3 State */
+ U2DS, 3,
+
+ offset (0x1e6e), /* USB3 D3 Control */
+ U3TD, 2,
+ , 1,
+ U3PD, 1,
+ offset (0x1e6f), /* USB3 D3 State */
+ U3DS, 3,
+
+ offset (0x1e70), /* SD D3 Control */
+ SDTD, 2,
+ , 1,
+ SDPD, 1,
+ , 1,
+ , 1,
+ SDRT, 1,
+ SDSC, 1,
+
+ offset (0x1e71), /* SD D3 State */
+ SDDS, 3,
+
+ offset (0x1e80), /* Shadow Register Request */
+ , 15,
+ RQ15, 1,
+ , 2,
+ RQ18, 1,
+ , 4,
+ RQ23, 1,
+ RQ24, 1,
+ , 5,
+ RQTY, 1,
+ offset (0x1e84), /* Shadow Register Status */
+ , 15,
+ SASR, 1, /* SATA 15 Shadow Reg Request Status Register */
+ , 2,
+ U2SR, 1, /* USB2 18 Shadow Reg Request Status Register */
+ , 4,
+ U3SR, 1, /* USB3 23 Shadow Reg Request Status Register */
+ SDSR, 1, /* SD 24 Shadow Reg Request Status Register */
+
+ offset (0x1ea0), /* PwrGood Control */
+ PG1A, 1,
+ PG2_, 1,
+ ,1,
+ U3PG, 1, /* Usb3 Power Good BIT3 */
+
+ offset (0x1ea3), /* PwrGood Control b[31:24] */
+ PGA3, 8 ,
+}
+
+OperationRegion(FCFG, SystemMemory, PCBA, 0x01000000)
+Field(FCFG, DwordAcc, NoLock, Preserve)
+{
+ /* XHCI */
+ Offset(0x00080010), /* Base address */
+ XHBA, 32,
+ Offset(0x0008002c), /* Subsystem ID / Vendor ID */
+ XH2C, 32,
+
+ Offset(0x00080048), /* Indirect PCI Index Register */
+ IDEX, 32,
+ DATA, 32,
+ Offset(0x00080054), /* PME Control / Status */
+ U_PS, 2,
+
+ /* EHCI */
+ Offset(0x00090004), /* Control */
+ , 1,
+ EHME, 1,
+ Offset(0x00090010), /* Base address */
+ EHBA, 32,
+ Offset(0x0009002c), /* Subsystem ID / Vendor ID */
+ EH2C, 32,
+ Offset(0x00090054), /* EHCI Spare 1 */
+ EH54, 8,
+ Offset(0x00090064), /* Misc Control 2 */
+ EH64, 8,
+
+ Offset(0x000900c4), /* PME Control / Status */
+ E_PS, 2,
+
+ /* LPC Bridge */
+ Offset(0x000a30cb), /* ClientRomProtect[31:24] */
+ , 7,
+ AUSS, 1, /* AutoSizeStart */
+}
+
+/*
+ * Arg0:device:
+ * 5=I2C0, 6=I2C1, 7=I2C2, 8=I2C3, 11=UART0, 12=UART1,
+ * 15=SATA, 18=EHCI, 23=xHCI, 24=SD
+ * Arg1:D-state
+ */
+Mutex (FDAS, 0) /* FCH Device AOAC Semophore */
+Method(FDDC, 2, Serialized)
+{
+ Acquire(FDAS, 0xffff)
+
+ if(LEqual(Arg1, 0)) {
+ Switch(ToInteger(Arg0)) {
+ Case(Package() {5, 15, 24}) {
+ Store(One, PG1A)
+ }
+ Case(Package() {6, 7, 8, 11, 12, 18}) {
+ Store(One, PG2_)
+ }
+ }
+ /* put device into D0 */
+ Switch(ToInteger(Arg0))
+ {
+ Case(5) {
+ Store(0x00, I0TD)
+ Store(One, I0PD)
+ Store(I0DS, Local0)
+ while(LNotEqual(Local0,0x7)) {
+ Store(I0DS, Local0)
+ }
+ }
+ Case(6) {
+ Store(0x00, I1TD)
+ Store(One, I1PD)
+ Store(I1DS, Local0)
+ while(LNotEqual(Local0,0x7)) {
+ Store(I1DS, Local0)
+ }
+ }
+ Case(7) {
+ Store(0x00, I2TD)
+ Store(One, I2PD)
+ Store(I2DS, Local0)
+ while(LNotEqual(Local0,0x7)) {
+ Store(I2DS, Local0)
+ }
+ }
+ Case(8) {Store(0x00, I3TD)
+ Store(One, I3PD)
+ Store(I3DS, Local0)
+ while(LNotEqual(Local0,0x7)) {
+ Store(I3DS, Local0)
+ }
+ }
+ Case(11) {
+ Store(0x00, U0TD)
+ Store(One, U0PD)
+ Store(U0DS, Local0)
+ while(LNotEqual(Local0,0x7)) {
+ Store(U0DS, Local0)
+ }
+ }
+ Case(12) {
+ Store(0x00, U1TD)
+ Store(One, U1PD)
+ Store(U1DS, Local0)
+ while(LNotEqual(Local0,0x7)) {
+ Store(U1DS, Local0)
+ }
+ }
+/* todo Case(15) { STD0()} */ /* SATA */
+ Case(18) { U2D0()} /* EHCI */
+ Case(23) { U3D0()} /* XHCI */
+ Case(24) { /* SD */
+ Store(0x00, SDTD)
+ Store(One, SDPD)
+ Store(SDDS, Local0)
+ while(LNotEqual(Local0,0x7)) {
+ Store(SDDS, Local0)
+ }
+ }
+ }
+ } else {
+ /* put device into D3cold */
+ Switch(ToInteger(Arg0))
+ {
+ Case(5) {
+ Store(Zero, I0PD)
+ Store(I0DS, Local0)
+ while(LNotEqual(Local0,0x0)) {
+ Store(I0DS, Local0)
+ }
+ Store(0x03, I0TD)
+ }
+ Case(6) {
+ Store(Zero, I1PD)
+ Store(I1DS, Local0)
+ while(LNotEqual(Local0,0x0)) {
+ Store(I1DS, Local0)
+ }
+ Store(0x03, I1TD)
+ }
+ Case(7) {
+ Store(Zero, I2PD)
+ Store(I2DS, Local0)
+ while(LNotEqual(Local0,0x0)) {
+ Store(I2DS, Local0)
+ }
+ Store(0x03, I2TD)}
+ Case(8) {
+ Store(Zero, I3PD)
+ Store(I3DS, Local0)
+ while(LNotEqual(Local0,0x0)) {
+ Store(I3DS, Local0)
+ }
+ Store(0x03, I3TD)
+ }
+ Case(11) {
+ Store(Zero, U0PD)
+ Store(U0DS, Local0)
+ while(LNotEqual(Local0,0x0)) {
+ Store(U0DS, Local0)
+ }
+ Store(0x03, U0TD)
+ }
+ Case(12) {
+ Store(Zero, U1PD)
+ Store(U1DS, Local0)
+ while(LNotEqual(Local0,0x0)) {
+ Store(U1DS, Local0)
+ }
+ Store(0x03, U1TD)
+ }
+/* todo Case(15) { STD3()} */ /* SATA */
+ Case(18) { U2D3()} /* EHCI */
+ Case(23) { U3D3()} /* XHCI */
+ Case(24) { /* SD */
+ Store(Zero, SDPD)
+ Store(SDDS, Local0)
+ while(LNotEqual(Local0,0x0)) {
+ Store(SDDS, Local0)
+ }
+ Store(0x03, SDTD)
+ }
+ }
+ /* Turn off Power */
+ if(LEqual(I0TD, 3)) {
+ if(LEqual(SATD, 3)) {
+ if(LEqual(SDTD, 3)) { Store(Zero, PG1A) }
+ }
+ }
+ if(LEqual(I1TD, 3)) {
+ if(LEqual(I2TD, 3)) {
+ if(LEqual(I3TD, 3)) {
+ if(LEqual(U0TD, 3)) {
+ if(LEqual(U1TD, 3)) {
+ if(LEqual(U2TD, 3)) {
+ Store(Zero, PG2_)
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ Release(FDAS)
+}
+
+Method(FPTS,0, Serialized) /* FCH _PTS */
+{
+ if(LEqual(\XHCE, one)) {
+ if(LNotEqual(U3TD, 0x03)) {
+ FDDC(23, 3)
+ }
+ }
+ if(LNotEqual(U2TD, 0x03)) {
+ FDDC(18, 3)
+ }
+}
+
+Method(FWAK,0, Serialized) /* FCH _WAK */
+{
+ if(LEqual(\XHCE, one)) {
+ if(LEqual(U3TD, 0x03)) {
+ FDDC(23, 0)
+ }
+ }
+ if(LEqual(U2TD, 0x03)) {
+ FDDC(18, 0)
+ }
+ if(LEqual(\UT0E, zero)) {
+ if(LNotEqual(U0TD, 0x03)) {
+ FDDC(11, 3)
+ }
+ }
+ if(LEqual(\UT1E, zero)) {
+ if(LNotEqual(U1TD, 0x03)) {
+ FDDC(12, 3)
+ }
+ }
+ if(LEqual(\IC0E, zero)) {
+ if(LNotEqual(I0TD, 0x03)) {
+ FDDC(5, 3)
+ }
+ }
+ if(LEqual(\IC1E, zero)) {
+ if(LNotEqual(I1TD, 0x03)) {
+ FDDC(6, 3)
+ }
+ }
+ if(LEqual(\IC2E, zero)) {
+ if(LNotEqual(I2TD, 0x03)) {
+ FDDC(7, 3)
+ }
+ }
+ if(LEqual(\IC3E, zero)) {
+ if(LNotEqual(I3TD, 0x03)) {
+ FDDC(8, 3)
+ }
+ }
+}
+
+/*
+ * Helper for setting a bit in AOACxA0 PwrGood Control
+ * Arg0: bit to set or clear
+ * Arg1: 0 = clear bit[Arg0], non-zero = set bit[Arg0]
+ */
+Method(PWGC,2, Serialized)
+{
+ And (PGA3, 0xdf, Local0) /* do SwUsb3SlpShutdown below */
+ if(Arg1) {
+ Or(Arg0, Local0, Local0)
+ } else {
+ Not(Arg0, Local1)
+ And(Local1, Local0, Local0)
+ }
+ Store(Local0, PGA3)
+ if(LEqual(Arg0, 0x20)) { /* if SwUsb3SlpShutdown */
+ Store(PGA3, Local0)
+ And(Arg0, Local0, Local0)
+ while(LNot(Local0)) { /* wait SwUsb3SlpShutdown to complete */
+ Store(PGA3, Local0)
+ And(Arg0, Local0, Local0)
+ }
+ }
+}
diff --git a/src/soc/amd/picasso/acpi/sleepstates.asl b/src/soc/amd/picasso/acpi/sleepstates.asl
new file mode 100644
index 0000000000..d4aabdb7af
--- /dev/null
+++ b/src/soc/amd/picasso/acpi/sleepstates.asl
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+Name(SSFG, 0x09)
+If (CONFIG(HAVE_ACPI_RESUME)) {
+ Store(0x0D, SSFG)
+}
+
+/* Supported sleep states: */
+Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
+
+If (And(SSFG, 0x01)) {
+ Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
+}
+If (And(SSFG, 0x02)) {
+ Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
+}
+If (And(SSFG, 0x04)) {
+ Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
+}
+If (And(SSFG, 0x08)) {
+ Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
+}
+
+Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl
new file mode 100644
index 0000000000..52c7ee6c00
--- /dev/null
+++ b/src/soc/amd/picasso/acpi/soc.asl
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device(PCI0) {
+ /* Describe the AMD Northbridge */
+ #include "northbridge.asl"
+
+ /* Describe the AMD Fusion Controller Hub */
+ #include "sb_pci0_fch.asl"
+}
+
+/* Describe PCI INT[A-H] for the Southbridge */
+#include "pci_int.asl"
+
+/* Describe the devices in the Southbridge */
+#include "sb_fch.asl"
+
+/* Add GPIO library */
+#include <soc/amd/common/acpi/gpio_bank_lib.asl>
diff --git a/src/soc/amd/picasso/acpi/usb.asl b/src/soc/amd/picasso/acpi/usb.asl
new file mode 100644
index 0000000000..f2ee8f6427
--- /dev/null
+++ b/src/soc/amd/picasso/acpi/usb.asl
@@ -0,0 +1,392 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* 0:12.0 - EHCI */
+Device(EHC0) {
+ Name(_ADR, 0x00120000)
+ Name(_PRW, Package() { 0xb, 3 })
+ Device (RHUB) {
+ Name (_ADR, Zero)
+ Device (HS01) { Name (_ADR, 1) }
+ Device (HS02) { Name (_ADR, 2) }
+ Device (HS03) { Name (_ADR, 3) }
+ Device (HS04) { Name (_ADR, 4) }
+ Device (HS05) { Name (_ADR, 5) }
+ Device (HS06) { Name (_ADR, 6) }
+ Device (HS07) { Name (_ADR, 7) }
+ Device (HS08) { Name (_ADR, 8) }
+ }
+
+ Name(_PR0, Package() { P0U2 }) /* Indicate support for D0 */
+ Name(_PR3, Package() { P3U2 }) /* Indicate support for D3cold */
+
+ Method(_S0W,0) {
+ Return(0)
+ }
+
+ Method(_S3W,0) {
+ Return(4)
+ }
+
+ Method(_S4W,0) {
+ Return(4)
+ }
+} /* end EHC0 */
+
+
+/* 0:10.0 - XHCI 0*/
+Device(XHC0) {
+ Name(_ADR, 0x00100000)
+ Name(_PRW, Package() { 0xb, 3 })
+ Device (SS01) { Name (_ADR, 1) }
+ Device (SS02) { Name (_ADR, 2) }
+ Device (SS03) { Name (_ADR, 3) }
+
+ Name(_PR0, Package() { P0U3 }) /* Indicate support for D0 */
+ Name(_PR3, Package() { P3U3 }) /* Indicate support for D3cold */
+
+ Method(_S0W,0) {
+ Return(0)
+ }
+
+ Method(_S3W,0) {
+ Return(4)
+ }
+
+ Method(_S4W,0) {
+ Return(4)
+ }
+
+} /* end XHC0 */
+
+Scope(\_SB)
+{
+ Name(XHD0, 0)
+ Name(XHD3, 0)
+ PowerResource(P0U3, 0, 0) {
+ Method(_STA) {
+ Return(XHD0)
+ }
+ Method(_ON) {
+ Store(0x01, XHD0)
+ }
+ Method(_OFF) {
+ Store(0x00, XHD0)
+ }
+ }
+ PowerResource(P3U3, 0, 0) {
+ Method(_STA) {
+ Return(XHD3)
+ }
+ Method(_ON) {
+ Store(0x01, XHD3)
+ }
+ Method(_OFF) {
+ Store(0x00, XHD3)
+ }
+ }
+
+ Name(EHD0, 0)
+ Name(EHD3, 0)
+ PowerResource(P0U2, 0, 0) {
+ Method(_STA) {
+ Return(EHD0)
+ }
+ Method(_ON) {
+ Store(0x01, EHD0)
+ }
+ Method(_OFF) {
+ Store(0x00, EHD0)
+ }
+ }
+ PowerResource(P3U2, 0, 0) {
+ Method(_STA) {
+ Return(EHD3)
+ }
+ Method(_ON) {
+ Store(0x01, EHD3)
+ }
+ Method(_OFF) {
+ Store(0x00, EHD3)
+ }
+ }
+}
+
+OperationRegion(EHMC, SystemMemory, EH10, 0x100)
+Field(EHMC, DwordAcc, NoLock, Preserve)
+{
+ Offset(0xb0),
+ , 5,
+ ESIM, 1,
+}
+
+Method(U2D3,0, Serialized)
+{
+ if (LNotEqual(EH10, Zero)) {
+ Store (EH10, EHBA)
+ Store (One, EHME)
+ Store (ESIM, SSIM)
+ }
+
+ if (LEqual(E_PS, 3)) {
+ Store (Zero, RQTY)
+ Store (One, RQ18)
+
+ Store (U2SR, Local0)
+ while (Local0) {
+ Store (U2SR, Local0)
+ }
+
+ Store (Zero, U2PD)
+
+ Store (U2DS, Local0)
+ while (LNotEqual(Local0, Zero)) {
+ Store (U2DS, Local0)
+ }
+
+ Store (0x03,U2TD)
+
+ if (LEqual(U3TD, 0x03)) { /* Shutdown USB2 PLL */
+ PWGC (0x40, 0)
+ Store (One, U2RP)
+ }
+ }
+}
+
+Method(U2D0,0, Serialized)
+{
+ PWGC (0x40, 1)
+ Store (Zero, U2RP)
+ Store (0x00,U2TD)
+
+ Store (Zero, U2TD)
+ Store (One, U2PD)
+
+ Store (U2DS, Local0)
+ while (LNotEqual(Local0,0x7)) {
+ Store (U2DS, Local0)
+ }
+
+ Store (One, RQTY)
+ Store (One, RQ18)
+ Store (U2SR, Local0)
+ while (LNot(Local0)) {
+ Store (U2SR, Local0)
+ }
+ Store (EHID, EH2C)
+
+
+ if (LNotEqual(EH10, Zero)) {
+ Store (EH10, EHBA)
+ Store (One, EHME)
+ Store (SSIM, ESIM)
+ }
+
+ Store (ES54, EH54)
+ Store (ES64, EH64)
+}
+
+Method(LXFW,3, Serialized) //Load Xhci FirmWare
+{
+ Store (One, FWLM) /* Firmware Load Mode */
+ Store (Arg0, ROAM) /* ROM/RAM */
+ Store (Arg1, UA04)
+ Store (Arg2, UA08)
+ Store (One, FPLS) /* Firmware Preload Start */
+ Store (FPLC, Local0) /* Firmware Preload Complete */
+ while (LNot(Local0)) {
+ Store (FPLC, Local0)
+ }
+ Store (Zero, FPLS)
+}
+
+Method(U3D3,0, Serialized)
+{
+ if (LEqual(U_PS, 3)) {
+ X0_S ()
+
+ Or (PGA3, 0x20, PGA3) /* SwUsb3SlpShutdown */
+ And (PGA3, 0x20, Local0)
+ while (LNot(Local0)) { /* wait for it to complete */
+ And (PGA3, 0x20, Local0)
+ }
+ Store (One, UD3P) /* U3P_D3Cold_PWRDN */
+
+ Store (Zero, U3PD) /* PwrOnDev */
+ Store (U3DS, Local0)
+ while (Local0) { /* RstBState, RefClkOkState, PwrRstBState */
+ Store (U3DS, Local0)
+ }
+
+ Store (0x3, U3TD) /* TargetedDeviceState */
+
+ Store (One, U3RP) /* USB3_RefClk_Pwdn */
+
+ if (Lequal(U2TD, 0x3)) { /* If EHCI targeted in D3cold */
+ And (PGA3, 0x9f, PGA3) /* SwUsb2S5RstB */
+ Store (One, U2RP) /* USB2_RefClk_Pwdn */
+ }
+ Store (Zero, U3PG) /* XhcPwrGood */
+ Store (One, U3PS) /* Usb3PowerSel */
+ }
+}
+
+Method(U3D0,0, Serialized)
+{
+ Store (Zero, U3PS) /* Usb3PowerSel */
+ Store (One, U3PG) /* XhcPwrGood */
+
+ Store (Zero, U2RP)
+ Store (Zero, U3RP)
+
+ And (PGA3, 0xdf, Local0)
+ Or (Local0, 0x40, Local0)
+ Store (Local0, PGA3) /* SwUsb2S5RstB */
+
+ Store (Zero, U3TD) /* TargetedDeviceState */
+ Store (One, U3PD) /* PwrOnDev */
+
+ Store (U3DS, Local0) /* wait for RstBState, RefClkOkState, PwrRstBState */
+ while (LNot(Lequal(Local0, 0x7))) {
+ Store (U3DS, Local0)
+ }
+
+ Store (U3PY, Local0) /* USB3 PHY Lock */
+ while (LNot(Local0)) {
+ Store (U3PY, Local0)
+ }
+
+ Store (Zero, U3PR) /* U3P_RESTORE_RESET */
+
+ Store (AUSS, Local0) /* AutoSizeStart */
+ if (LNotEqual(Local0,1)) {
+ Store(One, AUSS)
+ }
+ Store (AUSS, Local0)
+ while (LNotEqual(Local0,1)) {
+ Store (AUSS, Local0)
+ }
+
+ LXFW (1, FW00, FW01)
+ LXFW (0, FW02, FW03)
+
+ X0_R ()
+
+ Store (One, U3PR) /* U3P_RESTORE_RESET */
+ Store (Zero, UD3P) /* U3P_D3Cold_PWRDN */
+ Store (One, U3TD) /* TargetedDeviceState */
+}
+
+Name (SVBF, Buffer (0x1000) {0}) /* length from FchCarrizo.asl, new fields */
+CreateDWordField(SVBF, 0x000, S000) /* will be easier to add from there */
+CreateDWordField(SVBF, 0x004, S004)
+CreateDWordField(SVBF, 0x008, S008)
+CreateDWordField(SVBF, 0x00C, S00C)
+CreateDWordField(SVBF, 0x018, S018)
+CreateDWordField(SVBF, 0x01C, S01C)
+CreateDWordField(SVBF, 0x020, S020)
+CreateDWordField(SVBF, 0x030, S030)
+CreateDWordField(SVBF, 0x118, S118)
+CreateDWordField(SVBF, 0x158, S158)
+CreateDWordField(SVBF, 0x198, S198)
+CreateDWordField(SVBF, 0x1D8, S1D8)
+CreateDWordField(SVBF, 0x300, S300)
+CreateDWordField(SVBF, 0x304, S304)
+CreateDWordField(SVBF, 0x308, S308)
+CreateDWordField(SVBF, 0x30C, S30C)
+CreateDWordField(SVBF, 0x310, S310)
+CreateDWordField(SVBF, 0x428, S428)
+CreateDWordField(SVBF, 0x438, S438)
+CreateDWordField(SVBF, 0x43C, S43C)
+CreateDWordField(SVBF, 0x458, S458)
+CreateDWordField(SVBF, 0x468, S468)
+CreateDWordField(SVBF, 0x46C, S46C)
+CreateDWordField(SVBF, 0x470, S470)
+CreateDWordField(SVBF, 0x480, S480)
+CreateDWordField(SVBF, 0x484, S484)
+CreateDWordField(SVBF, 0x488, S488)
+CreateDWordField(SVBF, 0x48C, S48C)
+CreateDWordField(SVBF, 0x730, EHID) /* EHCI SSID */
+CreateDWordField(SVBF, 0x734, XHID) /* XHCI SSID */
+CreateByteField(SVBF, 0x740, ES54) /* EHCI PCIx54 */
+CreateByteField(SVBF, 0x741, ES64) /* EHCI PCIx64 */
+CreateDWordField(SVBF, 0x7B0, SSIM) /* EHCI SIM BIT */
+
+Method(X0_S,0)
+{
+ Store (XH2C, XHID)
+ Store (0x00000000, IDEX) Store (DATA, S000)
+ Store (0x00000004, IDEX) Store (DATA, S004)
+ Store (0x00000008, IDEX) Store (DATA, S008)
+ Store (0x0000000c, IDEX) Store (DATA, S00C)
+ Store (0x00000018, IDEX) Store (DATA, S018)
+ Store (0x0000001c, IDEX) Store (DATA, S01C)
+ Store (0x00000020, IDEX) Store (DATA, S020)
+ Store (0x00000030, IDEX) Store (DATA, S030)
+ Store (0x00000118, IDEX) Store (DATA, S118)
+ Store (0x00000158, IDEX) Store (DATA, S158)
+ Store (0x00000198, IDEX) Store (DATA, S198)
+ Store (0x000001d8, IDEX) Store (DATA, S1D8)
+ Store (0x00000300, IDEX) Store (DATA, S300)
+ Store (0x00000304, IDEX) Store (DATA, S304)
+ Store (0x00000308, IDEX) Store (DATA, S308)
+ Store (0x0000030c, IDEX) Store (DATA, S30C)
+ Store (0x00000310, IDEX) Store (DATA, S310)
+ Store (0x40000028, IDEX) Store (DATA, S428)
+ Store (0x40000038, IDEX) Store (DATA, S438)
+ Store (0x4000003c, IDEX) Store (DATA, S43C)
+ Store (0x40000058, IDEX) Store (DATA, S458)
+ Store (0x40000068, IDEX) Store (DATA, S468)
+ Store (0x4000006c, IDEX) Store (DATA, S46C)
+ Store (0x40000070, IDEX) Store (DATA, S470)
+ Store (0x40000080, IDEX) Store (DATA, S480)
+ Store (0x40000084, IDEX) Store (DATA, S484)
+ Store (0x40000088, IDEX) Store (DATA, S488)
+ Store (0x4000008c, IDEX) Store (DATA, S48C)
+}
+
+Method(X0_R,0)
+{
+ Store (XHID, XH2C)
+ Store (0x00000000, IDEX) Store (S000, DATA)
+ Store (0x00000004, IDEX) Store (S004, DATA)
+ Store (0x00000008, IDEX) Store (S008, DATA)
+ Store (0x0000000c, IDEX) Store (S00C, DATA)
+ Store (0x00000018, IDEX) Store (S018, DATA)
+ Store (0x0000001c, IDEX) Store (S01C, DATA)
+ Store (0x00000020, IDEX) Store (S020, DATA)
+ Store (0x00000030, IDEX) Store (S030, DATA)
+ Store (0x00000118, IDEX) Store (S118, DATA)
+ Store (0x00000158, IDEX) Store (S158, DATA)
+ Store (0x00000198, IDEX) Store (S198, DATA)
+ Store (0x000001d8, IDEX) Store (S1D8, DATA)
+ Store (0x00000300, IDEX) Store (S300, DATA)
+ Store (0x00000304, IDEX) Store (S304, DATA)
+ Store (0x00000308, IDEX) Store (S308, DATA)
+ Store (0x0000030c, IDEX) Store (S30C, DATA)
+ Store (0x00000310, IDEX) Store (S310, DATA)
+ Store (0x40000028, IDEX) Store (S428, DATA)
+ Store (0x40000038, IDEX) Store (S438, DATA)
+ Store (0x4000003c, IDEX) Store (S43C, DATA)
+ Store (0x40000058, IDEX) Store (S458, DATA)
+ Store (0x40000068, IDEX) Store (S468, DATA)
+ Store (0x4000006c, IDEX) Store (S46C, DATA)
+ Store (0x40000070, IDEX) Store (S470, DATA)
+ Store (0x40000080, IDEX) Store (S480, DATA)
+ Store (0x40000084, IDEX) Store (S484, DATA)
+ Store (0x40000088, IDEX) Store (S488, DATA)
+ Store (0x4000008c, IDEX) Store (S48C, DATA)
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-02 23:53:15 +0000