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Diffstat (limited to 'src/soc/amd/picasso/chip.h')
-rw-r--r--src/soc/amd/picasso/chip.h15
1 files changed, 0 insertions, 15 deletions
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index e84db3561e..d59a4c8207 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -105,19 +105,6 @@ struct soc_amd_picasso_config {
*/
u8 i2c_scl_reset;
struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT];
- enum {
- I2S_PINS_MAX_HDA = 0, /* HDA w/reset 3xSDI, SW w/Data0 */
- I2S_PINS_MAX_MHDA = 1, /* HDA no reset 3xSDI, SW w/Data0-1 */
- I2S_PINS_MIN_HDA = 2, /* HDA w/reset 1xSDI, SW w/Data0-2 */
- I2S_PINS_MIN_MHDA = 3, /* HDA no reset 1xSDI, SW w/Data0-3 */
- I2S_PINS_I2S_TDM = 4,
- I2S_PINS_UNCONF = 7, /* All pads will be input mode */
- } acp_pin_cfg;
-
- /* Enable ACP I2S wake feature (0 = disable, 1 = enable) */
- u8 acp_i2s_wake_enable;
- /* Enable ACP PME (0 = disable, 1 = enable) */
- u8 acp_pme_enable;
/* System config index */
uint8_t system_config;
@@ -270,8 +257,6 @@ struct soc_amd_picasso_config {
/* The array index is the general purpose PCIe clock output number. */
enum gpp_clk_req_setting gpp_clk_config[GPP_CLK_OUTPUT_COUNT];
- /* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */
- bool acp_i2s_use_external_48mhz_osc;
/* eDP phy tuning settings */
uint16_t edp_phy_override;