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-rw-r--r--src/soc/amd/picasso/include/soc/northbridge.h26
1 files changed, 0 insertions, 26 deletions
diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h
index 57373c9a08..667a49eb0c 100644
--- a/src/soc/amd/picasso/include/soc/northbridge.h
+++ b/src/soc/amd/picasso/include/soc/northbridge.h
@@ -20,28 +20,6 @@
#include <device/device.h>
#include <types.h>
-/* D0F0 - Root Complex */
-
-/* NB IOAPIC registers */
-#define NB_IOAPIC_INDEX 0xf8
-#define NB_IOAPIC_DATA 0xfc
-#define NB_IOAPIC_FEATURE_CTRL 0x00
-#define NB_IOAPIC_ADDRESS_LOW 0x01
-#define NB_IOAPIC_ADDRESS_HIGH 0x02
-#define NB_IOAPIC_GBIF_IRR 0x0f
-#define NB_IOAPIC_BR0_IRR 0x10
-#define NB_IOAPIC_BR1_IRR 0x11
-#define NB_IOAPIC_BR2_IRR 0x12
-#define NB_IOAPIC_BR3_IRR 0x13
-#define NB_IOAPIC_BR4_IRR 0x14
-#define NB_IOAPIC_APG_IRR 0x2f
-#define NB_IOAPIC_SPG_IRR 0x30
-#define NB_IOAPIC_SER_IRQ_IRR 0x31
-#define NB_IOAPIC_SCRATCH0 0x3e
-#define NB_IOAPIC_SCRATCH1 0x3f
-
-#define AP_SCRATCH_REG NB_IOAPIC_SCRATCH0
-
/* D1F1 - HDA Configuration Registers */
#define HDA_DEV_CTRL_STATUS 0x60
#define HDA_NO_SNOOP_EN BIT(11)
@@ -104,10 +82,6 @@ void amd_initcpuio(void);
void domain_enable_resources(struct device *dev);
void domain_set_resources(struct device *dev);
void fam15_finalize(void *chip_info);
-uint32_t nb_ioapic_read(unsigned int index);
-void nb_ioapic_write(unsigned int index, uint32_t value);
-void *get_ap_entry_ptr(void);
-void set_ap_entry_ptr(void *entry);
void set_warm_reset_flag(void);
int is_warm_reset(void);