diff options
Diffstat (limited to 'src/soc/amd/picasso/romstage.c')
| -rw-r--r-- | src/soc/amd/picasso/romstage.c | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 5d1ed1877c..904f556202 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -32,7 +32,6 @@ #include <soc/northbridge.h> #include <soc/romstage.h> #include <soc/southbridge.h> -#include <amdblocks/psp.h> #include "chip.h" @@ -41,28 +40,6 @@ void __weak mainboard_romstage_entry(int s3_resume) /* By default, don't do anything */ } -static void load_smu_fw1(void) -{ - u32 base, limit, cmd; - - /* Open a posted hole from 0x80000000 : 0xfed00000-1 */ - base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE; - limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8); - pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit); - pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base); - - /* Preload a value into "BAR3" and enable it */ - pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE); - pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN); - - /* Enable memory access and master */ - cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND); - cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; - pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd); - - psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw"); -} - static void agesa_call(void) { post_code(0x37); @@ -94,9 +71,6 @@ asmlinkage void car_stage_entry(void) console_init(); - if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) - load_smu_fw1(); - mainboard_romstage_entry(s3_resume); bsp_agesa_call(); @@ -143,9 +117,6 @@ asmlinkage void car_stage_entry(void) post_code(0x61); } - post_code(0x42); - psp_notify_dram(); - post_code(0x43); if (cbmem_recovery(s3_resume)) printk(BIOS_CRIT, "Failed to recover cbmem\n"); |