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-rw-r--r--src/soc/amd/picasso/include/soc/cpu.h2
-rw-r--r--src/soc/amd/picasso/southbridge.c3
2 files changed, 2 insertions, 3 deletions
diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h
index 99b31c3bfe..fd9c5fee48 100644
--- a/src/soc/amd/picasso/include/soc/cpu.h
+++ b/src/soc/amd/picasso/include/soc/cpu.h
@@ -3,8 +3,6 @@
#ifndef __PICASSO_CPU_H__
#define __PICASSO_CPU_H__
-#define CSTATE_BASE_REG 0xc0010073
-
int get_cpu_count(void);
void check_mca(void);
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 123eca772a..a18f5a37bd 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -3,6 +3,7 @@
#include <console/console.h>
#include <device/mmio.h>
#include <bootstate.h>
+#include <cpu/amd/msr.h>
#include <cpu/x86/smm.h>
#include <cpu/x86/msr.h>
#include <device/device.h>
@@ -318,7 +319,7 @@ static void sb_init_acpi_ports(void)
/* CpuControl is in \_SB.CP00, 6 bytes */
cst_addr.hi = 0;
cst_addr.lo = ACPI_CPU_CONTROL;
- wrmsr(CSTATE_BASE_REG, cst_addr);
+ wrmsr(MSR_CSTATE_ADDRESS, cst_addr);
if (CONFIG(HAVE_SMI_HANDLER)) {
/* APMC - SMI Command Port */