diff options
Diffstat (limited to 'src/soc/amd/stoneyridge/acpi')
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/cpu.asl | 22 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/globalnvs.asl | 47 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/lpc.asl | 7 |
3 files changed, 64 insertions, 12 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl index aae3287ba6..32dad76d56 100644 --- a/src/soc/amd/stoneyridge/acpi/cpu.asl +++ b/src/soc/amd/stoneyridge/acpi/cpu.asl @@ -13,14 +13,18 @@ * GNU General Public License for more details. */ +/* Required function by EC, Notify OS to re-read CPU tables */ +Method (PNOT) +{ +} + /* * Processor Object - * */ Scope (\_PR) { /* define processor scope */ Processor( P000, /* name space name */ - 0, /* Unique number for this processor */ + 0, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { @@ -28,49 +32,49 @@ Scope (\_PR) { /* define processor scope */ Processor( P001, /* name space name */ - 1, /* Unique number for this processor */ + 1, /* Unique number for this processor */ 0x0810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { } Processor( P002, /* name space name */ - 2, /* Unique number for this processor */ + 2, /* Unique number for this processor */ 0x0810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { } Processor( P003, /* name space name */ - 3, /* Unique number for this processor */ + 3, /* Unique number for this processor */ 0x0810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { } Processor( P004, /* name space name */ - 4, /* Unique number for this processor */ + 4, /* Unique number for this processor */ 0x0810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { } Processor( P005, /* name space name */ - 5, /* Unique number for this processor */ + 5, /* Unique number for this processor */ 0x0810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { } Processor( P006, /* name space name */ - 6, /* Unique number for this processor */ + 6, /* Unique number for this processor */ 0x0810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { } Processor( P007, /* name space name */ - 7, /* Unique number for this processor */ + 7, /* Unique number for this processor */ 0x0810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl new file mode 100644 index 0000000000..bf0ed55249 --- /dev/null +++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * NOTE: The layout of the GNVS structure below must match the layout in + * soc/amd/stoneyridge/include/soc/nvs.h !!! + * + */ + +External (NVSA) + +OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) +Field (GNVS, ByteAcc, NoLock, Preserve) +{ + /* Miscellaneous */ + Offset (0x00), + PCNT, 8, // 0x00 - Processor Count + PPCM, 8, // 0x01 - Max PPC State + LIDS, 8, // 0x02 - LID State + PWRS, 8, // 0x03 - AC Power State + DPTE, 8, // 0x04 - Enable DPTF + CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console + PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index + GPEI, 64, // 0x11 - 0x18 - GPE Wake Source + NHLA, 64, // 0x19 - 0x20 - NHLT Address + NHLL, 32, // 0x21 - 0x24 - NHLT Length + PRT0, 32, // 0x25 - 0x28 - PERST_0 Address + SCDP, 8, // 0x29 - SD_CD GPIO portid + SCDO, 8, // 0x2A - GPIO pad offset relative to the community + /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ + Offset (0x100), + #include <vendorcode/google/chromeos/acpi/gnvs.asl> +} diff --git a/src/soc/amd/stoneyridge/acpi/lpc.asl b/src/soc/amd/stoneyridge/acpi/lpc.asl index 783a2c952c..a41357a306 100644 --- a/src/soc/amd/stoneyridge/acpi/lpc.asl +++ b/src/soc/amd/stoneyridge/acpi/lpc.asl @@ -14,8 +14,9 @@ */ /* 0:14.3 - LPC */ -Device(LIBR) { +Device(LPCB) { Name(_ADR, 0x00140003) + /* Method(_INI) { * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") } */ /* End Method(_SB.SBRDG._INI) */ @@ -37,7 +38,7 @@ Device(LIBR) { ) }) - Method(_CRS,0,NotSerialized) + Method(_CRS,0,Serialized) { CreateDwordField(^CRS,^BAR0._BAS,SPIB) // Field to hold SPI base address CreateDwordField(^CRS,^BAR0._LEN,SPIL) // Field to hold SPI address length @@ -100,4 +101,4 @@ Device(LIBR) { IRQNoFlags(){13} }) } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ -} /* end LIBR */ +} /* end LPCB */ |