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Diffstat (limited to 'src/soc/amd/stoneyridge/i2c.c')
-rw-r--r--src/soc/amd/stoneyridge/i2c.c99
1 files changed, 99 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c
index e99f3509ff..c3e5539e19 100644
--- a/src/soc/amd/stoneyridge/i2c.c
+++ b/src/soc/amd/stoneyridge/i2c.c
@@ -13,12 +13,16 @@
* GNU General Public License for more details.
*/
+#include <device/mmio.h>
#include <arch/acpi.h>
#include <console/console.h>
+#include <delay.h>
#include <drivers/i2c/designware/dw_i2c.h>
+#include <amdblocks/acpimmio.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/southbridge.h>
+#include <soc/i2c.h>
#include "chip.h"
#define I2C_BUS_ADDRESS(x) (I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * (x))
@@ -140,3 +144,98 @@ struct device_operations stoneyridge_i2c_mmio_ops = {
.acpi_name = i2c_acpi_name,
.acpi_fill_ssdt_generator = dw_i2c_acpi_fill_ssdt,
};
+
+/*
+ * I2C pins are open drain with external pull up, so in order to bit bang them
+ * all, SCL pins must become GPIO inputs with no pull, then they need to be
+ * toggled between input-no-pull and output-low. This table is for the initial
+ * conversion of all SCL pins to input with no pull.
+ */
+static const struct soc_amd_gpio i2c_2_gpi[] = {
+ PAD_GPI(I2C0_SCL_PIN, PULL_NONE),
+ PAD_GPI(I2C1_SCL_PIN, PULL_NONE),
+ PAD_GPI(I2C2_SCL_PIN, PULL_NONE),
+ PAD_GPI(I2C3_SCL_PIN, PULL_NONE),
+};
+#define saved_pins_count ARRAY_SIZE(i2c_2_gpi)
+
+/*
+ * To program I2C pins without destroying their programming, the registers
+ * that will be changed need to be saved first.
+ */
+static void save_i2c_pin_registers(uint8_t gpio,
+ struct soc_amd_i2c_save *save_table)
+{
+ uint32_t *gpio_ptr;
+
+ gpio_ptr = (uint32_t *)gpio_get_address(gpio);
+ save_table->mux_value = iomux_read8(gpio);
+ save_table->control_value = read32(gpio_ptr);
+}
+
+static void restore_i2c_pin_registers(uint8_t gpio,
+ struct soc_amd_i2c_save *save_table)
+{
+ uint32_t *gpio_ptr;
+
+ gpio_ptr = (uint32_t *)gpio_get_address(gpio);
+ iomux_write8(gpio, save_table->mux_value);
+ iomux_read8(gpio);
+ write32(gpio_ptr, save_table->control_value);
+ read32(gpio_ptr);
+}
+
+/* Slaves to be reset are controlled by devicetree register i2c_scl_reset */
+void sb_reset_i2c_slaves(void)
+{
+ const struct soc_amd_stoneyridge_config *cfg;
+ const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
+ struct soc_amd_i2c_save save_table[saved_pins_count];
+ uint8_t i, j, control;
+
+ if (!dev || !dev->chip_info)
+ return;
+ cfg = dev->chip_info;
+ control = cfg->i2c_scl_reset & GPIO_I2C_MASK;
+ if (control == 0)
+ return;
+
+ /* Save and reprogram I2C SCL pins */
+ for (i = 0; i < saved_pins_count; i++)
+ save_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]);
+ sb_program_gpios(i2c_2_gpi, saved_pins_count);
+
+ /*
+ * Toggle SCL back and forth 9 times under 100KHz. A single read is
+ * needed after the writes to force the posted write to complete.
+ */
+ for (j = 0; j < 9; j++) {
+ if (control & GPIO_I2C0_SCL)
+ write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_LOW);
+ if (control & GPIO_I2C1_SCL)
+ write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_LOW);
+ if (control & GPIO_I2C2_SCL)
+ write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_LOW);
+ if (control & GPIO_I2C3_SCL)
+ write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_LOW);
+
+ read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */
+ udelay(4); /* 4usec gets 85KHz for 1 pin, 70KHz for 4 pins */
+
+ if (control & GPIO_I2C0_SCL)
+ write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_HIGH);
+ if (control & GPIO_I2C1_SCL)
+ write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_HIGH);
+ if (control & GPIO_I2C2_SCL)
+ write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_HIGH);
+ if (control & GPIO_I2C3_SCL)
+ write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_HIGH);
+
+ read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */
+ udelay(4);
+ }
+
+ /* Restore I2C pins. */
+ for (i = 0; i < saved_pins_count; i++)
+ restore_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]);
+}