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-rw-r--r--src/soc/amd/stoneyridge/include/soc/iomap.h4
-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h3
2 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h
index 341d97d687..beb2bc83d3 100644
--- a/src/soc/amd/stoneyridge/include/soc/iomap.h
+++ b/src/soc/amd/stoneyridge/include/soc/iomap.h
@@ -52,9 +52,13 @@
#define ACPI_SMI_CTL_PORT 0xb2
#define STONEYRIDGE_ACPI_IO_BASE CONFIG_STONEYRIDGE_ACPI_IO_BASE
#define ACPI_PM_EVT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x00) /* 4 bytes */
+#define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) /* 2 bytes */
+#define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */
#define ACPI_PM1_CNT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x04) /* 2 bytes */
#define ACPI_CPU_CONTROL (STONEYRIDGE_ACPI_IO_BASE + 0x08) /* 6 bytes */
#define ACPI_GPE0_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */
+#define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */
+#define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */
#define ACPI_PM_TMR_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */
#define SMB_BASE_ADDR 0xb00
#define PM2_INDEX 0xcd0
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 10b1f4328b..1750547dea 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -353,6 +353,9 @@
#define FCH_AOAC_STAT0 BIT(6)
#define FCH_AOAC_STAT1 BIT(7)
+#define PM1_LIMIT 16
+#define GPE0_LIMIT 28
+
struct stoneyridge_aoac {
int enable;
int status;