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Diffstat (limited to 'src/soc/amd/stoneyridge/lpc.c')
-rw-r--r--src/soc/amd/stoneyridge/lpc.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c
index 10f4a4b7df..eb512817b6 100644
--- a/src/soc/amd/stoneyridge/lpc.c
+++ b/src/soc/amd/stoneyridge/lpc.c
@@ -76,11 +76,12 @@ static void lpc_init(device_t dev)
pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte);
/*
- * bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12.
- * todo: verify against BKDG
+ * IMC is not used, but some of its registers and ports need to be
+ * programmed/accessed. So enable CPU access to them. This fixes
+ * SPI_CS# timing issue when running at 66MHz.
*/
byte = pci_read_config8(dev, LPC_HOST_CONTROL);
- byte |= SPI_FROM_HOST_PREFETCH_EN | 1 << 3;
+ byte |= IMC_PAGE_FROM_HOST_EN | IMC_PORT_FROM_HOST_EN;
pci_write_config8(dev, LPC_HOST_CONTROL, byte);
cmos_check_update_date();