diff options
Diffstat (limited to 'src/soc/amd/stoneyridge/smbus.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/smbus.c | 58 |
1 files changed, 25 insertions, 33 deletions
diff --git a/src/soc/amd/stoneyridge/smbus.c b/src/soc/amd/stoneyridge/smbus.c index e890c470a9..aef3edf5e6 100644 --- a/src/soc/amd/stoneyridge/smbus.c +++ b/src/soc/amd/stoneyridge/smbus.c @@ -13,9 +13,6 @@ * GNU General Public License for more details. */ -#ifndef _STONEYRIDGE_SMBUS_C_ -#define _STONEYRIDGE_SMBUS_C_ - #include <io.h> #include <stdint.h> #include <soc/smbus.h> @@ -45,11 +42,10 @@ static int smbus_wait_until_done(u32 smbus_io_base) val = inb(smbus_io_base + SMBHSTSTAT); val &= 0x1f; /* mask off reserved bits */ - if (val & 0x1c) { + if (val & 0x1c) return -5; /* error */ - } if (val == 0x02) { - outb(val, smbus_io_base + SMBHSTSTAT); /* clear status */ + outb(val, smbus_io_base + SMBHSTSTAT); /* clear sts */ return 0; } } while (--loops); @@ -60,22 +56,20 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device) { u8 byte; - if (smbus_wait_until_ready(smbus_io_base) < 0) { + if (smbus_wait_until_ready(smbus_io_base) < 0) return -2; /* not ready */ - } /* set the device I'm talking too */ outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); byte = inb(smbus_io_base + SMBHSTCTRL); byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ + byte |= (1 << 2) | (1 << 6); /* Byte data R/W cmd, start the command */ outb(byte, smbus_io_base + SMBHSTCTRL); /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { + if (smbus_wait_until_done(smbus_io_base) < 0) return -3; /* timeout or error */ - } /* read results of transaction */ byte = inb(smbus_io_base + SMBHSTCMD); @@ -87,9 +81,8 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) { u8 byte; - if (smbus_wait_until_ready(smbus_io_base) < 0) { + if (smbus_wait_until_ready(smbus_io_base) < 0) return -2; /* not ready */ - } /* set the command... */ outb(val, smbus_io_base + SMBHSTCMD); @@ -99,13 +92,12 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) byte = inb(smbus_io_base + SMBHSTCTRL); byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ + byte |= (1 << 2) | (1 << 6); /* Byte data R/W cmd, start command */ outb(byte, smbus_io_base + SMBHSTCTRL); /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { + if (smbus_wait_until_done(smbus_io_base) < 0) return -3; /* timeout or error */ - } return 0; } @@ -115,9 +107,8 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, { u8 byte; - if (smbus_wait_until_ready(smbus_io_base) < 0) { + if (smbus_wait_until_ready(smbus_io_base) < 0) return -2; /* not ready */ - } /* set the command/address... */ outb(address & 0xff, smbus_io_base + SMBHSTCMD); @@ -127,13 +118,12 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, byte = inb(smbus_io_base + SMBHSTCTRL); byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ + byte |= (1 << 3) | (1 << 6); /* Byte data R/W cmd, start command */ outb(byte, smbus_io_base + SMBHSTCTRL); /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { + if (smbus_wait_until_done(smbus_io_base) < 0) return -3; /* timeout or error */ - } /* read results of transaction */ byte = inb(smbus_io_base + SMBHSTDAT0); @@ -146,9 +136,8 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, { u8 byte; - if (smbus_wait_until_ready(smbus_io_base) < 0) { + if (smbus_wait_until_ready(smbus_io_base) < 0) return -2; /* not ready */ - } /* set the command/address... */ outb(address & 0xff, smbus_io_base + SMBHSTCMD); @@ -161,13 +150,12 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, byte = inb(smbus_io_base + SMBHSTCTRL); byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ + byte |= (1 << 3) | (1 << 6); /* Byte data R/W cmd, start command */ outb(byte, smbus_io_base + SMBHSTCTRL); /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { + if (smbus_wait_until_done(smbus_io_base) < 0) return -3; /* timeout or error */ - } return 0; } @@ -188,8 +176,11 @@ void alink_ab_indx(u32 reg_space, u32 reg_addr, tmp &= ~mask; tmp |= val; - /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */ - outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ + // printk(BIOS_DEBUG, "about write %x, index=%x", tmp, + // (reg_space&0x3)<<29 | reg_addr); + + /* probably we dont have to do it again. */ + outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); outl(tmp, AB_DATA); outl(0, AB_INDX); } @@ -210,8 +201,11 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, tmp &= ~mask; tmp |= val; - //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr); - outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ + //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, + // (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr); + + /* probably we dont have to do it again. */ + outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); outl(tmp, AB_DATA); outl(0, AB_INDX); } @@ -219,8 +213,7 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, /* space = 0: AX_INDXC, AX_DATAC * space = 1: AX_INDXP, AX_DATAP */ -void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, - u32 mask, u32 val) +void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val) { u32 tmp; @@ -243,4 +236,3 @@ void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, outl(tmp, AB_DATA); outl(0, AB_INDX); } -#endif |