diff options
Diffstat (limited to 'src/soc/amd/stoneyridge')
| -rw-r--r-- | src/soc/amd/stoneyridge/cpu.c | 4 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/lpc.c | 22 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/northbridge.c | 25 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 3 |
4 files changed, 24 insertions, 30 deletions
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index c140fca7db..6cb59a955d 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -55,8 +55,8 @@ static void pre_mp_init(void) static int get_cpu_count(void) { - struct device *nb = dev_find_slot(0, HT_DEVFN); - return (pci_read_config16(nb, D18F0_CPU_CNT) & CPU_CNT_MASK) + 1; + return (pci_read_config16(SOC_NB_DEV, D18F0_CPU_CNT) & CPU_CNT_MASK) + + 1; } static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c index 6833db6a8a..317574b36c 100644 --- a/src/soc/amd/stoneyridge/lpc.c +++ b/src/soc/amd/stoneyridge/lpc.c @@ -38,32 +38,30 @@ static void lpc_init(struct device *dev) { u8 byte; u32 dword; - struct device *sm_dev; /* * Enable the LPC Controller * SMBus register 0x64 is not defined in public datasheet. */ - sm_dev = dev_find_slot(0, SMBUS_DEVFN); - dword = pci_read_config32(sm_dev, 0x64); + dword = pci_read_config32(SOC_SMBUS_DEV, 0x64); dword |= 1 << 20; - pci_write_config32(sm_dev, 0x64, dword); + pci_write_config32(SOC_SMBUS_DEV, 0x64, dword); /* Initialize isa dma */ isa_dma_init(); /* Enable DMA transaction on the LPC bus */ - byte = pci_read_config8(dev, LPC_PCI_CONTROL); + byte = pci_read_config8(SOC_SMBUS_DEV, LPC_PCI_CONTROL); byte |= LEGACY_DMA_EN; - pci_write_config8(dev, LPC_PCI_CONTROL, byte); + pci_write_config8(SOC_SMBUS_DEV, LPC_PCI_CONTROL, byte); /* Disable the timeout mechanism on LPC */ - byte = pci_read_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE); + byte = pci_read_config8(SOC_SMBUS_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); byte &= ~LPC_SYNC_TIMEOUT_COUNT_ENABLE; - pci_write_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE, byte); + pci_write_config8(SOC_SMBUS_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, byte); /* Disable LPC MSI Capability */ - byte = pci_read_config8(dev, LPC_MISC_CONTROL_BITS); + byte = pci_read_config8(SOC_SMBUS_DEV, LPC_MISC_CONTROL_BITS); /* BIT 1 is not defined in public datasheet. */ byte &= ~(1 << 1); @@ -73,15 +71,15 @@ static void lpc_init(struct device *dev) * interrupt and visit LPC. */ byte &= ~LPC_NOHOG; - pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte); + pci_write_config8(SOC_SMBUS_DEV, LPC_MISC_CONTROL_BITS, byte); /* * Enable hand-instance of the pulse generator and SPI * controller prefetch of flash. */ - byte = pci_read_config8(dev, LPC_HOST_CONTROL); + byte = pci_read_config8(SOC_SMBUS_DEV, LPC_HOST_CONTROL); byte |= PREFETCH_EN_SPI_FROM_HOST | T_START_ENH; - pci_write_config8(dev, LPC_HOST_CONTROL, byte); + pci_write_config8(SOC_SMBUS_DEV, LPC_HOST_CONTROL, byte); cmos_check_update_date(); diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index a2ae52c09e..5fb28c028c 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -48,27 +48,25 @@ static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 tempreg; - struct device *addr_map = dev_find_slot(0, ADDR_DEVFN); /* io range allocation. Limit */ tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) | ((io_max & 0xf0) << (12 - 4)); - pci_write_config32(addr_map, reg + 4, tempreg); + pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg); tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); /* base: ISA and VGA ? */ - pci_write_config32(addr_map, reg, tempreg); + pci_write_config32(SOC_ADDR_DEV, reg, tempreg); } static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max) { u32 tempreg; - struct device *addr_map = dev_find_slot(0, ADDR_DEVFN); /* io range allocation. Limit */ tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00); - pci_write_config32(addr_map, reg + 4, tempreg); + pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00); - pci_write_config32(addr_map, reg, tempreg); + pci_write_config32(SOC_ADDR_DEV, reg, tempreg); } static void read_resources(struct device *dev) @@ -154,7 +152,7 @@ static void create_vga_resource(struct device *dev) printk(BIOS_DEBUG, "VGA: %s has VGA device\n", dev_path(dev)); /* Route A0000-BFFFF, IO 3B0-3BB 3C0-3DF */ - pci_write_config32(dev_find_slot(0, ADDR_DEVFN), 0xf4, 1); + pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE); } static void set_resources(struct device *dev) @@ -379,17 +377,16 @@ void amd_initcpuio(void) void fam15_finalize(void *chip_info) { - struct device *dev; u32 value; - dev = dev_find_slot(0, GNB_DEVFN); /* clear IoapicSbFeatureEn */ - pci_write_config32(dev, 0xf8, 0); - pci_write_config32(dev, 0xfc, 5); /* TODO: move it to dsdt.asl */ + + /* TODO: move IOAPIC code to dsdt.asl */ + pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, 0); + pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, 5); /* disable No Snoop */ - dev = dev_find_slot(0, HDA0_DEVFN); - value = pci_read_config32(dev, HDA_DEV_CTRL_STATUS); + value = pci_read_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS); value &= ~HDA_NO_SNOOP_EN; - pci_write_config32(dev, HDA_DEV_CTRL_STATUS, value); + pci_write_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS, value); } void domain_read_resources(struct device *dev) diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 326ea613b0..35cf253b7b 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -892,7 +892,7 @@ static void set_sb_final_nvs(void) uintptr_t xhci_fw; uintptr_t fwaddr; size_t fwsize; - const struct device *sd, *sata, *ehci; + const struct device *sd, *sata; struct global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (gnvs == NULL) @@ -925,7 +925,6 @@ static void set_sb_final_nvs(void) gnvs->fw02 = fwaddr + XHCI_FW_BOOTRAM_SIZE; gnvs->fw03 = fwsize << 16; - ehci = dev_find_slot(0, EHCI1_DEVFN); gnvs->eh10 = pci_read_config32(SOC_EHCI1_DEV, PCI_BASE_ADDRESS_0) & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; } |