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-rw-r--r--src/soc/amd/stoneyridge/romstage.c13
1 files changed, 2 insertions, 11 deletions
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 0d65ef6c82..4032d3f8b8 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -85,8 +85,6 @@ asmlinkage void car_stage_entry(void)
{
struct postcar_frame pcf;
uintptr_t top_of_ram;
- uintptr_t smm_base;
- size_t smm_size;
msr_t base, mask;
msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT;
@@ -172,15 +170,8 @@ asmlinkage void car_stage_entry(void)
/* Cache the memory-mapped boot media. */
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
- /*
- * Cache the TSEG region at the top of ram. This region is
- * not restricted to SMM mode until SMM has been relocated.
- * By setting the region to cacheable it provides faster access
- * when relocating the SMM handler as well as using the TSEG
- * region for other purposes.
- */
- smm_region(&smm_base, &smm_size);
- postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
+ /* Cache the TSEG region */
+ postcar_enable_tseg_cache(&pcf);
post_code(0x45);
run_postcar_phase(&pcf);