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-rw-r--r--src/soc/amd/common/block/cpu/Kconfig8
-rw-r--r--src/soc/amd/common/block/cpu/car/exit_car.S3
2 files changed, 7 insertions, 4 deletions
diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig
index 86cc77194c..5941599df0 100644
--- a/src/soc/amd/common/block/cpu/Kconfig
+++ b/src/soc/amd/common/block/cpu/Kconfig
@@ -3,6 +3,8 @@ config SOC_AMD_COMMON_BLOCK_CAR
default n
help
This option allows the SOC to use a standard AMD cache-as-ram (CAR)
- implementation. CAR setup is built into bootblock and teardown in
- romstage. If it is not used the system must implement these functions
- separately.
+ implementation. CAR setup is built into bootblock and teardown is
+ in postcar. The teardown procedure does not preserve the stack so
+ it may not be appropriate for a romstage implementation without
+ additional consideration. If this option is not used, the SOC must
+ implement these functions separately.
diff --git a/src/soc/amd/common/block/cpu/car/exit_car.S b/src/soc/amd/common/block/cpu/car/exit_car.S
index ac36cb0e4f..f9d056e599 100644
--- a/src/soc/amd/common/block/cpu/car/exit_car.S
+++ b/src/soc/amd/common/block/cpu/car/exit_car.S
@@ -20,6 +20,7 @@
.globl chipset_teardown_car
chipset_teardown_car:
+ pop %esp
/* Disable cache */
movl %cr0, %eax
@@ -33,4 +34,4 @@ chipset_teardown_car:
andl $(~(CR0_CD | CR0_NW)), %eax
movl %eax, %cr0
- ret
+ jmp *%esp