4 files changed, 2 insertions, 10 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 2df0b6a120..fd2a2053fb 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -56,6 +56,7 @@ config CPU_SPECIFIC_OPTIONS
 	select UDK_2017_BINDING
 	select HAVE_CF9_RESET
 	select SUPPORT_CPU_UCODE_IN_CBFS
+	select ACPI_NO_SMI_GNVS
 
 config MEMLAYOUT_LD_FILE
 	string
diff --git a/src/soc/amd/picasso/smi.c b/src/soc/amd/picasso/smi.c
index ba36e65da6..125dde601c 100644
--- a/src/soc/amd/picasso/smi.c
+++ b/src/soc/amd/picasso/smi.c
@@ -11,11 +11,6 @@
 #include <soc/southbridge.h>
 #include <soc/smi.h>
 
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
-	printk(BIOS_DEBUG, "%s STUB!!!\n", __func__);
-}
-
 /** Set the EOS bit and enable SMI generation from southbridge */
 void global_smi_enable(void)
 {
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 47642a9fda..9bb5604391 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -46,6 +46,7 @@ config CPU_SPECIFIC_OPTIONS
 	select HAVE_SMI_HANDLER
 	select SSE2
 	select RTC
+	select ACPI_NO_SMI_GNVS
 
 config AMD_APU_STONEYRIDGE
 	bool
diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c
index a3473aafc5..fb6d3484ad 100644
--- a/src/soc/amd/stoneyridge/smi.c
+++ b/src/soc/amd/stoneyridge/smi.c
@@ -10,11 +10,6 @@
 #include <soc/southbridge.h>
 #include <soc/smi.h>
 
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
-	printk(BIOS_DEBUG, "%s STUB!!!\n", __func__);
-}
-
 /** Set the EOS bit and enable SMI generation from southbridge */
 void global_smi_enable(void)
 {