summaryrefslogtreecommitdiff
path: root/src/soc/broadcom
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/broadcom')
-rw-r--r--src/soc/broadcom/cygnus/Kconfig8
-rwxr-xr-xsrc/soc/broadcom/cygnus/ddr_init.c21
-rwxr-xr-xsrc/soc/broadcom/cygnus/include/soc/config.h4
-rw-r--r--src/soc/broadcom/cygnus/include/soc/halapis/ddr_regs.h62
4 files changed, 95 insertions, 0 deletions
diff --git a/src/soc/broadcom/cygnus/Kconfig b/src/soc/broadcom/cygnus/Kconfig
index 821b2dc39c..b2f06133a9 100644
--- a/src/soc/broadcom/cygnus/Kconfig
+++ b/src/soc/broadcom/cygnus/Kconfig
@@ -51,6 +51,14 @@ config CYGNUS_DDR800
bool "DDR Speed at 800MHz"
default y
+config CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE
+ bool "Enable DDR auto self-refresh"
+ default y
+ help
+ Warning: M0 expects that auto self-refresh is enabled. Modify
+ with caution.
+
+
config CYGNUS_SHMOO_REUSE_DDR_32BIT
bool "Indicate if DDR width is 32-bit"
default n
diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c
index 27a981ee66..9aac58f7e9 100755
--- a/src/soc/broadcom/cygnus/ddr_init.c
+++ b/src/soc/broadcom/cygnus/ddr_init.c
@@ -1490,6 +1490,27 @@ void ddr_init2(void)
}
}
+#if CONFIG_CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE
+#if (DDR_AUTO_SELF_REFRESH_IDLE_COUNT > 0) & (DDR_AUTO_SELF_REFRESH_IDLE_COUNT <= 0xff)
+ /* Enable auto self-refresh */
+ reg32_set_bits((unsigned int *)DDR_DENALI_CTL_57,
+ 0x2 << DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_R |
+ 0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R );
+
+ reg32_set_bits((unsigned int *)DDR_DENALI_CTL_58,
+ DDR_AUTO_SELF_REFRESH_IDLE_COUNT << DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R);
+#else
+ #error DDR_AUTO_SELF_REFRESH_IDLE_COUNT out of range
+#endif
+#else
+ /* Disable auto-self refresh */
+ reg32_clear_bits((unsigned int *)DDR_DENALI_CTL_57,
+ 0x2 << DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_R |
+ 0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R );
+ reg32_clear_bits((unsigned int *)DDR_DENALI_CTL_58,
+ 0xff << DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R );
+#endif
+
/* Start the DDR */
reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_00, 0x01);
diff --git a/src/soc/broadcom/cygnus/include/soc/config.h b/src/soc/broadcom/cygnus/include/soc/config.h
index 7511827338..0ba09e372b 100755
--- a/src/soc/broadcom/cygnus/include/soc/config.h
+++ b/src/soc/broadcom/cygnus/include/soc/config.h
@@ -29,4 +29,8 @@
#else
#define SDI_NUM_ROWS 65536
#endif
+
+/* Idle count (in units of 1024 cycles) before auto entering self-refresh */
+#define DDR_AUTO_SELF_REFRESH_IDLE_COUNT 16
+
#endif /* __SOC_BROADCOM_CYGNUS_CONFIG_H__ */
diff --git a/src/soc/broadcom/cygnus/include/soc/halapis/ddr_regs.h b/src/soc/broadcom/cygnus/include/soc/halapis/ddr_regs.h
index 80cd9690e4..32668d1d86 100644
--- a/src/soc/broadcom/cygnus/include/soc/halapis/ddr_regs.h
+++ b/src/soc/broadcom/cygnus/include/soc/halapis/ddr_regs.h
@@ -114,6 +114,68 @@
#define DDR_DENALI_CTL_56_DATAMASK 0xffffffff
#define DDR_DENALI_CTL_56_RDWRMASK 0x00000000
#define DDR_DENALI_CTL_56_RESETVALUE 0x0
+#define DDR_DENALI_CTL_57 0x180100e4
+#define DDR_DENALI_CTL_57_BASE 0x0e4
+#define DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_L 26
+#define DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_R 24
+#define DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_WIDTH 3
+#define DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_RESETVALUE 0x0
+#define DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_L 18
+#define DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R 16
+#define DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_WIDTH 3
+#define DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_RESETVALUE 0x0
+#define DDR_DENALI_CTL_57__LP_ARB_STATE_L 11
+#define DDR_DENALI_CTL_57__LP_ARB_STATE_R 8
+#define DDR_DENALI_CTL_57__LP_ARB_STATE_WIDTH 4
+#define DDR_DENALI_CTL_57__LP_ARB_STATE_RESETVALUE 0x0
+#define DDR_DENALI_CTL_57__LP_STATE_L 5
+#define DDR_DENALI_CTL_57__LP_STATE_R 0
+#define DDR_DENALI_CTL_57__LP_STATE_WIDTH 6
+#define DDR_DENALI_CTL_57__LP_STATE_RESETVALUE 0x20
+#define DDR_DENALI_CTL_57__RESERVED_0_L 31
+#define DDR_DENALI_CTL_57__RESERVED_0_R 27
+#define DDR_DENALI_CTL_57__RESERVED_1_L 23
+#define DDR_DENALI_CTL_57__RESERVED_1_R 19
+#define DDR_DENALI_CTL_57__RESERVED_2_L 15
+#define DDR_DENALI_CTL_57__RESERVED_2_R 12
+#define DDR_DENALI_CTL_57__RESERVED_3_L 7
+#define DDR_DENALI_CTL_57__RESERVED_3_R 6
+#define DDR_DENALI_CTL_57__RESERVED_L 31
+#define DDR_DENALI_CTL_57__RESERVED_R 27
+#define DDR_DENALI_CTL_57_WIDTH 27
+#define DDR_DENALI_CTL_57__WIDTH 27
+#define DDR_DENALI_CTL_57_ALL_L 26
+#define DDR_DENALI_CTL_57_ALL_R 0
+#define DDR_DENALI_CTL_57__ALL_L 26
+#define DDR_DENALI_CTL_57__ALL_R 0
+#define DDR_DENALI_CTL_57_DATAMASK 0x07070f3f
+#define DDR_DENALI_CTL_57_RDWRMASK 0xf8f8f0c0
+#define DDR_DENALI_CTL_57_RESETVALUE 0x20
+#define DDR_DENALI_CTL_58 0x180100e8
+#define DDR_DENALI_CTL_58_BASE 0x0e8
+#define DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_L 31
+#define DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R 24
+#define DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_WIDTH 8
+#define DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_RESETVALUE 0x00
+#define DDR_DENALI_CTL_58__LP_AUTO_PD_IDLE_L 19
+#define DDR_DENALI_CTL_58__LP_AUTO_PD_IDLE_R 8
+#define DDR_DENALI_CTL_58__LP_AUTO_PD_IDLE_WIDTH 12
+#define DDR_DENALI_CTL_58__LP_AUTO_PD_IDLE_RESETVALUE 0x000
+#define DDR_DENALI_CTL_58__LP_AUTO_MEM_GATE_EN_L 1
+#define DDR_DENALI_CTL_58__LP_AUTO_MEM_GATE_EN_R 0
+#define DDR_DENALI_CTL_58__LP_AUTO_MEM_GATE_EN_WIDTH 2
+#define DDR_DENALI_CTL_58__LP_AUTO_MEM_GATE_EN_RESETVALUE 0x0
+#define DDR_DENALI_CTL_58__RESERVED_L 23
+#define DDR_DENALI_CTL_58__RESERVED_R 20
+#define DDR_DENALI_CTL_58_WIDTH 32
+#define DDR_DENALI_CTL_58__WIDTH 32
+#define DDR_DENALI_CTL_58_ALL_L 31
+#define DDR_DENALI_CTL_58_ALL_R 0
+#define DDR_DENALI_CTL_58__ALL_L 31
+#define DDR_DENALI_CTL_58__ALL_R 0
+#define DDR_DENALI_CTL_58_DATAMASK 0xff0fff03
+#define DDR_DENALI_CTL_58_RDWRMASK 0x00f000fc
+#define DDR_DENALI_CTL_58_RESETVALUE 0x0
#define DDR_DENALI_CTL_175 0x180102bc
#define DDR_DENALI_CTL_175_BASE 0x2bc