summaryrefslogtreecommitdiff
path: root/src/soc/imgtec/pistachio/monotonic_timer.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/imgtec/pistachio/monotonic_timer.c')
-rw-r--r--src/soc/imgtec/pistachio/monotonic_timer.c19
1 files changed, 16 insertions, 3 deletions
diff --git a/src/soc/imgtec/pistachio/monotonic_timer.c b/src/soc/imgtec/pistachio/monotonic_timer.c
index 99c147b7c2..c2408b0649 100644
--- a/src/soc/imgtec/pistachio/monotonic_timer.c
+++ b/src/soc/imgtec/pistachio/monotonic_timer.c
@@ -23,6 +23,9 @@
#include <arch/cpu.h>
#include <soc/cpu.h>
+#define PISTACHIO_CLOCK_SWITCH 0xB8144200
+#define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002
+
static int get_count_mhz_freq(void)
{
static unsigned count_mhz_freq;
@@ -30,10 +33,20 @@ static int get_count_mhz_freq(void)
if (!count_mhz_freq) {
if (IMG_PLATFORM_ID() != IMG_PLATFORM_ID_SILICON)
count_mhz_freq = 25; /* FPGA board */
- /*
- * Will need some means of finding out the counter
- * frequency on a real SOC
+ else {
+ /* If MIPS PLL external bypass bit is set, it means
+ * that the MIPS PLL is already set up to work at a
+ * frequency of 550 MHz; otherwise, the crystal is
+ * used with a frequency of 52 MHz
*/
+ if (read32(PISTACHIO_CLOCK_SWITCH) &
+ MIPS_EXTERN_PLL_BYPASS_MASK)
+ /* Half MIPS PLL freq. */
+ count_mhz_freq = 275;
+ else
+ /* Half Xtal freq. */
+ count_mhz_freq = 26;
+ }
}
return count_mhz_freq;
}