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-rw-r--r--src/soc/imgtec/pistachio/Kconfig31
-rw-r--r--src/soc/imgtec/pistachio/Makefile.inc2
-rw-r--r--src/soc/imgtec/pistachio/cbmem.c3
-rw-r--r--src/soc/imgtec/pistachio/memlayout.ld38
4 files changed, 41 insertions, 33 deletions
diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig
index 2e8b700007..70e5741cf1 100644
--- a/src/soc/imgtec/pistachio/Kconfig
+++ b/src/soc/imgtec/pistachio/Kconfig
@@ -35,10 +35,6 @@ config BOOTBLOCK_CPU_INIT
string
default "soc/imgtec/pistachio/bootblock.c"
-config BOOTBLOCK_BASE
- hex
- default 0x9b000000
-
config CBFS_ROM_OFFSET
hex
default 0x4100
@@ -48,31 +44,4 @@ config CBFS_HEADER_ROM_OFFSET
hex
default 0x4000
-config ROMSTAGE_BASE
- hex
- default 0x9b004000
- help
- The address where romstage is supposed to be loaded, right above the
- bootblock.
-
-config CBMEM_CONSOLE_PRERAM_BASE
- hex "memory address of the CBMEM console buffer"
- default 0x9b00f800
- help
- Allocate 4KB to the pre-ram console buffer, we should be able to use
- GRAM eventually and have a much larger buffer.
-
-config BOOTBLOCK_STACK_BOTTOM
- hex
- default 0x9b00e000
- help
- This allocates 6KB of stack space. One needs to verify that this is
- sufficient.
-
-config BOOTBLOCK_STACK_TOP
- hex
- default CBMEM_CONSOLE_PRERAM_BASE
- help
- Bootblock stack starts immediately under the CBMEM console buffer,
- stack location might be changed by romstage.
endif
diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc
index b91bb1b59a..d052c8f435 100644
--- a/src/soc/imgtec/pistachio/Makefile.inc
+++ b/src/soc/imgtec/pistachio/Makefile.inc
@@ -51,5 +51,5 @@ $(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf
# Create a complete bootblock which will start up the system
$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw $(BIMGTOOL)
@printf " BIMGTOOL $(subst $(obj)/,,$(@))\n"
- $(BIMGTOOL) $< $@ $(CONFIG_BOOTBLOCK_BASE)
+ $(BIMGTOOL) $< $@ $(call loadaddr,bootblock)
diff --git a/src/soc/imgtec/pistachio/cbmem.c b/src/soc/imgtec/pistachio/cbmem.c
index 5fb6c0e7bd..373d4f853d 100644
--- a/src/soc/imgtec/pistachio/cbmem.c
+++ b/src/soc/imgtec/pistachio/cbmem.c
@@ -21,9 +21,10 @@
#include <cbmem.h>
#include <stdlib.h>
+#include <symbols.h>
void *cbmem_top(void)
{
uintptr_t top = MIN(CONFIG_DRAM_SIZE_MB, 256) << 20;
- return (void *)(top + CONFIG_SYS_SDRAM_BASE);
+ return _dram + top;
}
diff --git a/src/soc/imgtec/pistachio/memlayout.ld b/src/soc/imgtec/pistachio/memlayout.ld
new file mode 100644
index 0000000000..21c3d73d5f
--- /dev/null
+++ b/src/soc/imgtec/pistachio/memlayout.ld
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <memlayout.h>
+
+#include <arch/header.ld>
+
+/* TODO: This should be revised by someone who understands the SoC better. */
+
+SECTIONS
+{
+ CBFS_CACHE(0x0, 0) /* TODO: fix this, it was already broken before!!! */
+
+ DRAM_START(0x80000000)
+ RAMSTAGE(0x80000000, 128K)
+
+ /* TODO: Does this SoC use SRAM? Add SRAM_START() and SRAM_END(). */
+ BOOTBLOCK(0x9B000000, 16K)
+ ROMSTAGE(0x9B004000, 40K)
+ STACK(0x9B00E000, 6K)
+ PRERAM_CBMEM_CONSOLE(0x9B00F800, 3K)
+}