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Diffstat (limited to 'src/soc/intel/alderlake/chip.h')
-rw-r--r--src/soc/intel/alderlake/chip.h8
1 files changed, 0 insertions, 8 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 428fd4deeb..38d9671f60 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -146,12 +146,6 @@ struct soc_intel_alderlake_config {
/* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */
uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];
- /* Integrated Sensor */
- uint8_t PchIshEnable;
-
- /* Heci related */
- uint8_t Heci3Enabled;
-
/* Gfx related */
enum {
IGD_SM_0MB = 0x00,
@@ -178,8 +172,6 @@ struct soc_intel_alderlake_config {
uint8_t InternalGfx;
uint8_t SkipExtGfxScan;
- uint32_t GraphicsConfigPtr;
-
/* HeciEnabled decides the state of Heci1 at end of boot
* Setting to 0 (default) disables Heci1 and hides the device from OS */
uint8_t HeciEnabled;