3 files changed, 10 insertions, 8 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index dc9e823f93..1a3f0724ae 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -136,6 +136,9 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
 	int
 	default 120
 
+config CPU_XTAL_HZ
+	default 38400000
+
 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 	int
 	default 133
diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c
index ee8051d568..e6a21c170e 100644
--- a/src/soc/intel/alderlake/cpu.c
+++ b/src/soc/intel/alderlake/cpu.c
@@ -111,15 +111,17 @@ static void configure_dca_cap(void)
 
 static void enable_pm_timer_emulation(void)
 {
-	/* ACPI PM timer emulation */
 	msr_t msr;
+
+	if (!CONFIG_CPU_XTAL_HZ)
+		return;
+
 	/*
 	 * The derived frequency is calculated as follows:
-	 * (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
-	 * Back solve the multiplier so the 3.579545MHz ACPI timer
-	 * frequency is used.
+	 * (clock * msr[63:32]) >> 32 = target frequency.
+	 * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
 	 */
-	msr.hi = (3579545ULL << 32) / CTC_FREQ;
+	msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
 	/* Set PM1 timer IO port and enable */
 	msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
 			EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
diff --git a/src/soc/intel/alderlake/include/soc/cpu.h b/src/soc/intel/alderlake/include/soc/cpu.h
index 3c11183831..71c2f47605 100644
--- a/src/soc/intel/alderlake/include/soc/cpu.h
+++ b/src/soc/intel/alderlake/include/soc/cpu.h
@@ -19,7 +19,4 @@
 #define C9_POWER	0xc8
 #define C10_POWER	0xc8
 
-/* Common Timer Copy (CTC) frequency - 38.4MHz. */
-#define CTC_FREQ	38400000
-
 #endif