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-rw-r--r--src/soc/intel/apollolake/include/soc/ramstage.h26
1 files changed, 26 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/ramstage.h b/src/soc/intel/apollolake/include/soc/ramstage.h
new file mode 100644
index 0000000000..287f2ff945
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/ramstage.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
+ * Copyright (C) 2019 9elements Agency GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_APOLLOLAKE_RAMSTAGE_H_
+#define _SOC_APOLLOLAKE_RAMSTAGE_H_
+
+#include <fsp/api.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig);
+
+#endif /* _SOC_APOLLOLAKE_RAMSTAGE_H_ */