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-rw-r--r--src/soc/intel/apollolake/memmap.c31
1 files changed, 0 insertions, 31 deletions
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c
index 7b60270488..f828024d29 100644
--- a/src/soc/intel/apollolake/memmap.c
+++ b/src/soc/intel/apollolake/memmap.c
@@ -15,14 +15,8 @@
* GNU General Public License for more details.
*/
-#include <arch/romstage.h>
-#include <assert.h>
#include <cbmem.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/smm.h>
-#include <device/pci.h>
#include <soc/systemagent.h>
-#include <soc/pci_devs.h>
#include "chip.h"
@@ -42,28 +36,3 @@ void *cbmem_top(void)
return tolum;
}
-
-void smm_region(uintptr_t *start, size_t *size)
-{
- *start = sa_get_tseg_base();
- *size = sa_get_tseg_size();
-}
-
-void fill_postcar_frame(struct postcar_frame *pcf)
-{
- uintptr_t top_of_ram;
-
- /*
- * We need to make sure ramstage will be run cached. At this point exact
- * location of ramstage in cbmem is not known. Instruct postcar to cache
- * 16 megs under cbmem top which is a safe bet to cover ramstage.
- */
- top_of_ram = (uintptr_t) cbmem_top();
- /* cbmem_top() needs to be at least 16 MiB aligned */
- assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram);
- postcar_frame_add_mtrr(pcf, top_of_ram - 16*MiB, 16*MiB,
- MTRR_TYPE_WRBACK);
-
- /* Cache the TSEG region */
- postcar_enable_tseg_cache(pcf);
-}