diff options
Diffstat (limited to 'src/soc/intel/apollolake')
| -rw-r--r-- | src/soc/intel/apollolake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/bootblock/bootblock.c | 11 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/elog.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/iomap.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/pcr_ids.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/pm.h | 7 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/smbus.h | 28 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/pmutil.c | 21 |
8 files changed, 50 insertions, 25 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index bc1a80575d..dcf1b1a0af 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -93,6 +93,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_TIMER + select SOC_INTEL_COMMON_BLOCK_TCO select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_XDCI select SOC_INTEL_COMMON_BLOCK_XHCI diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index ce89f133ee..cf3e8395de 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2016-2018 Intel Corp. * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -25,6 +25,7 @@ #include <intelblocks/rtc.h> #include <intelblocks/systemagent.h> #include <intelblocks/pmclib.h> +#include <intelblocks/tco.h> #include <intelblocks/uart.h> #include <soc/iomap.h> #include <soc/cpu.h> @@ -87,8 +88,6 @@ static void enable_pmcbar(void) void bootblock_soc_early_init(void) { - uint32_t reg; - enable_pmcbar(); /* Clear global reset promotion bit */ @@ -110,10 +109,8 @@ void bootblock_soc_early_init(void) /* Initialize GPE for use as interrupt status */ pmc_gpe_init(); - /* Stop TCO timer */ - reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); - reg |= TCO_TMR_HLT; - outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); + /* Program TCO Timer Halt */ + tco_configure(); /* Use Nx and paging to prevent the frontend from writing back dirty * cache-as-ram lines to backing store that doesn't exist when the L1I diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c index 361b041f5c..b03d5e65c2 100644 --- a/src/soc/intel/apollolake/elog.c +++ b/src/soc/intel/apollolake/elog.c @@ -21,6 +21,7 @@ #include <intelblocks/pmclib.h> #include <soc/pm.h> #include <soc/pci_devs.h> +#include <soc/smbus.h> #include <stdint.h> static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) @@ -80,7 +81,7 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps) /* TCO Timeout */ if (ps->prev_sleep_state != ACPI_S3 && - ps->tco_sts & TCO_TIMEOUT) + ps->tco1_sts & TCO_TIMEOUT) elog_add_event(ELOG_TYPE_TCO_RESET); /* Power Button Override */ diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index b1cf3da88a..8e2986d8b7 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -29,6 +29,9 @@ #define ACPI_BASE_SIZE 0x100 #define R_ACPI_PM1_TMR 0x8 +#define TCO_BASE_ADDRESS (ACPI_BASE_ADDRESS + 0x60) +#define TCO_BASE_SIZE 0x20 + /* CST Range (R/W) IO port block size */ #define PMG_IO_BASE_CST_RNG_BLK_SIZE 0x5 /* ACPI PMIO Offset to C-state register*/ diff --git a/src/soc/intel/apollolake/include/soc/pcr_ids.h b/src/soc/intel/apollolake/include/soc/pcr_ids.h index 4af8f2c23e..264704c755 100644 --- a/src/soc/intel/apollolake/include/soc/pcr_ids.h +++ b/src/soc/intel/apollolake/include/soc/pcr_ids.h @@ -40,5 +40,6 @@ #define PID_TUNIT 0x52 #define PID_PSF3 0xC6 +#define PID_DMI 0x00 /* Reserved */ #endif /* SOC_INTEL_APL_PCR_H */ diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index c4f1d1b39c..61c97cebb5 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -131,10 +131,6 @@ #define GPE_CNTL 0x50 #define DEVACT_STS 0x4c -#define TCO_STS 0x64 -#define TCO_TIMEOUT (1 << 3) -#define TCO1_CNT 0x68 -#define TCO_TMR_HLT (1 << 11) #define GPE0_REG_MAX 4 #define GPE0_REG_SIZE 32 @@ -240,7 +236,8 @@ struct chipset_power_state { uint32_t pm1_cnt; uint32_t gpe0_sts[GPE0_REG_MAX]; uint32_t gpe0_en[GPE0_REG_MAX]; - uint32_t tco_sts; + uint16_t tco1_sts; + uint16_t tco2_sts; uint32_t prsts; uint32_t gen_pmcon1; uint32_t gen_pmcon2; diff --git a/src/soc/intel/apollolake/include/soc/smbus.h b/src/soc/intel/apollolake/include/soc/smbus.h new file mode 100644 index 0000000000..4b252d61a9 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/smbus.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_SMBUS_H_ +#define _SOC_APOLLOLAKE_SMBUS_H_ + +/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ +#define TCO1_STS 0x04 +#define TCO_TIMEOUT (1 << 3) +#define TCO2_STS 0x06 +#define TCO_STS_SECOND_TO (1 << 1) +#define TCO1_CNT 0x08 +#define TCO_LOCK (1 << 12) +#define TCO_TMR_HLT (1 << 11) + +#endif diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index c36d84d8de..812a16a23a 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -28,11 +28,13 @@ #include <intelblocks/msr.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> +#include <intelblocks/tco.h> #include <rules.h> #include <soc/iomap.h> #include <soc/cpu.h> #include <soc/pci_devs.h> #include <soc/pm.h> +#include <soc/smbus.h> #include <timer.h> #include <security/vboot/vbnv.h> #include "chip.h" @@ -133,15 +135,6 @@ const char *const *soc_std_gpe_sts_array(size_t *a) return gpe_sts_bits; } -uint32_t soc_reset_tco_status(void) -{ - uint32_t tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); - uint32_t tco_en = inl(ACPI_BASE_ADDRESS + TCO1_CNT); - - outl(tco_sts, ACPI_BASE_ADDRESS + TCO_STS); - return tco_sts & tco_en; -} - void soc_clear_pm_registers(uintptr_t pmc_bar) { uint32_t gen_pmcon1; @@ -173,14 +166,18 @@ void soc_fill_power_state(struct chipset_power_state *ps) { uintptr_t pmc_bar0 = read_pmc_mmio_bar(); - ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); + ps->tco1_sts = tco_read_reg(TCO1_STS); + ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->prsts = read32((void *)(pmc_bar0 + PRSTS)); ps->gen_pmcon1 = read32((void *)(pmc_bar0 + GEN_PMCON1)); ps->gen_pmcon2 = read32((void *)(pmc_bar0 + GEN_PMCON2)); ps->gen_pmcon3 = read32((void *)(pmc_bar0 + GEN_PMCON3)); - printk(BIOS_DEBUG, "prsts: %08x tco_sts: %08x\n", - ps->prsts, ps->tco_sts); + printk(BIOS_DEBUG, "prsts: %08x\n", + ps->prsts); + printk(BIOS_DEBUG, "tco_sts: %04x %04x\n", + ps->tco1_sts, ps->tco2_sts); printk(BIOS_DEBUG, "gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n", ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3); |