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-rw-r--r--src/soc/intel/apollolake/acpi.c5
-rw-r--r--src/soc/intel/apollolake/acpi/globalnvs.asl5
-rw-r--r--src/soc/intel/apollolake/acpi/northbridge.asl25
-rw-r--r--src/soc/intel/apollolake/include/soc/iomap.h5
-rw-r--r--src/soc/intel/apollolake/include/soc/nvs.h7
5 files changed, 29 insertions, 18 deletions
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index 7163884365..46c7b6ce0a 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2016 Intel Corp.
+ * Copyright (C) 2016-2020 Intel Corp.
* Copyright (C) 2017-2019 Siemens AG
* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
*
@@ -127,6 +127,9 @@ void acpi_create_gnvs(struct global_nvs_t *gnvs)
if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX))
sgx_fill_gnvs(gnvs);
+
+ /* Fill in Above 4GB MMIO resource */
+ sa_fill_gnvs(gnvs);
}
uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en,
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl
index 4aad29c81a..1db373d484 100644
--- a/src/soc/intel/apollolake/acpi/globalnvs.asl
+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2016 Intel Corp.
+ * Copyright (C) 2016-2020 Intel Corp.
* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
@@ -45,6 +45,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
EPCS, 8, // 0x2C - SGX Enabled status
EMNA, 64, // 0x2D - 0x34 EPC base address
ELNG, 64, // 0x35 - 0x3C EPC Length
+ E4GM, 8, // 0x3D - Enable above 4GB MMIO Resource
+ A4GB, 64, // 0x3E - 0x45 Base of above 4GB MMIO Resource
+ A4GS, 64, // 0x46 - 0x4D Length of above 4GB MMIO Resource
/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
Offset (0x100),
diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl
index 027e2a623c..ff146ec9db 100644
--- a/src/soc/intel/apollolake/acpi/northbridge.asl
+++ b/src/soc/intel/apollolake/acpi/northbridge.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2016 Intel Corp.
+ * Copyright (C) 2016-2020 Intel Corp.
* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
@@ -15,7 +15,6 @@
* GNU General Public License for more details.
*/
-#define BASE_64GB 0x1000000000
Name(_HID, EISAID("PNP0A08")) /* PCIe */
Name(_CID, EISAID("PNP0A03")) /* PCI */
@@ -115,18 +114,18 @@ Method (_CRS, 0, Serialized)
Add(Subtract(GMAX, GMIN), 1, GLEN)
/* Patch PM02 range based on Memory Size */
- CreateQwordField (MCRS, PM02._MIN, MMIN)
- CreateQwordField (MCRS, PM02._MAX, MMAX)
- CreateQwordField (MCRS, PM02._LEN, MLEN)
-
- Store (\_SB.PCI0.MCHC.TUUD, Local0)
-
- If (LLessEqual (Local0, BASE_64GB))
- {
- Store (0, MMIN)
- Store (0, MLEN)
+ If (LEqual (A4GS, 0)) {
+ CreateQwordField (MCRS, PM02._LEN, MSEN)
+ Store (0, MSEN)
+ } Else {
+ CreateQwordField (MCRS, PM02._MIN, MMIN)
+ CreateQwordField (MCRS, PM02._MAX, MMAX)
+ CreateQwordField (MCRS, PM02._LEN, MLEN)
+ /* Set 64bit MMIO resource base and length */
+ Store (A4GS, MLEN)
+ Store (A4GB, MMIN)
+ Subtract (Add (MMIN, MLEN), 1, MMAX)
}
- Subtract (Add (MMIN, MLEN), 1, MMAX)
Return (MCRS)
}
diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h
index 3057fbe33e..e2fa46299e 100644
--- a/src/soc/intel/apollolake/include/soc/iomap.h
+++ b/src/soc/intel/apollolake/include/soc/iomap.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2015-2020 Intel Corp.
* (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
@@ -60,4 +60,7 @@
#define EARLY_I2C_BASE_ADDRESS 0xfe020000
#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
+#define ABOVE_4GB_MEM_BASE_ADDRESS (128ULL * GiB)
+#define ABOVE_4GB_MEM_BASE_SIZE (64ULL * GiB)
+
#endif /* _SOC_APOLLOLAKE_IOMAP_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index 6c37d5977b..9cdeee1ad2 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015-2017 Intel Corp.
+ * Copyright (C) 2015-2020 Intel Corp.
* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
@@ -47,7 +47,10 @@ typedef struct global_nvs_t {
uint8_t ecps; /* 0x2C - SGX Enabled status */
uint64_t emna; /* 0x2D - 0x34 EPC base address */
uint64_t elng; /* 0x35 - 0x3C EPC Length */
- uint8_t unused[195];
+ uint8_t e4gm; /* 0x3D - Enable above 4GB MMIO Resource */
+ uint64_t a4gb; /* 0x3E - 0x45 Base of above 4GB MMIO Resource */
+ uint64_t a4gs; /* 0x46 - 0x4D Length of above 4GB MMIO Resource */
+ uint8_t unused[178];
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;