diff options
Diffstat (limited to 'src/soc/intel/baytrail/romstage')
| -rw-r--r-- | src/soc/intel/baytrail/romstage/pmc.c | 36 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/romstage/raminit.c | 5 |
2 files changed, 36 insertions, 5 deletions
diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c index 49a80111f5..c58a42c37e 100644 --- a/src/soc/intel/baytrail/romstage/pmc.c +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -19,11 +19,16 @@ #include <stddef.h> #include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci_def.h> #include <baytrail/iomap.h> #include <baytrail/iosf.h> +#include <baytrail/lpc.h> #include <baytrail/pci_devs.h> #include <baytrail/pmc.h> #include <baytrail/romstage.h> +#include "../chip.h" void tco_disable(void) { @@ -38,13 +43,34 @@ void tco_disable(void) void punit_init(void) { uint32_t reg; + uint8_t rid; + const struct device *dev; + const struct soc_intel_baytrail_config *cfg = NULL; + rid = pci_read_config8(IOSF_PCI_DEV, REVID); + dev = dev_find_slot(0, PCI_DEVFN(SOC_DEV, SOC_FUNC)); + + if (dev) + cfg = dev->chip_info; + + reg = iosf_punit_read(SB_BIOS_CONFIG); /* Write bits 17:16 of SB_BIOS_CONFIG in the PUNIT. */ - reg = SB_BIOS_CONFIG_PERF_MODE | SB_BIOS_CONFIG_PDM_MODE; - pci_write_config32(IOSF_PCI_DEV, MDR_REG, reg); - reg = IOSF_OPCODE(IOSF_OP_WRITE_PMC) | IOSF_PORT(IOSF_PORT_PMC) | - IOSF_REG(SB_BIOS_CONFIG) | IOSF_BYTE_EN_2; - pci_write_config32(IOSF_PCI_DEV, MCR_REG, reg); + reg |= SB_BIOS_CONFIG_PERF_MODE | SB_BIOS_CONFIG_PDM_MODE; + /* Configure VR low power mode for C0 and above. */ + if (rid >= RID_C_STEPPING_START && cfg != NULL && + (cfg->vnn_ps2_enable || cfg->vcc_ps2_enable)) { + printk(BIOS_DEBUG, "Enabling VR PS2 mode: "); + if (cfg->vnn_ps2_enable) { + reg |= SB_BIOS_CONFIG_PS2_EN_VNN; + printk(BIOS_DEBUG, "VNN "); + } + if (cfg->vcc_ps2_enable) { + reg |= SB_BIOS_CONFIG_PS2_EN_VCC; + printk(BIOS_DEBUG, "VCC "); + } + printk(BIOS_DEBUG, "\n"); + } + iosf_punit_write(SB_BIOS_CONFIG, reg); /* Write bits 1:0 of BIOS_RESET_CPL in the PUNIT. */ reg = BIOS_RESET_CPL_ALL_DONE | BIOS_RESET_CPL_RESET_DONE; diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 752a49b1ff..a18f312386 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -121,6 +121,11 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) mp->console_out = &send_to_console; mp->prev_sleep_state = prev_sleep_state; mp->rmt_enabled = IS_ENABLED(CONFIG_MRC_RMT); + + /* Default to 2GiB IO hole. */ + if (!mp->io_hole_mb) + mp->io_hole_mb = 2048; + if (recovery_mode_enabled()) { printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); } else if (!mrc_cache_get_current(&cache)) { |