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-rw-r--r--src/soc/intel/baytrail/memmap.c15
-rw-r--r--src/soc/intel/baytrail/romstage/romstage.c13
2 files changed, 15 insertions, 13 deletions
diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c
index 015f13c503..d9f6160dfc 100644
--- a/src/soc/intel/baytrail/memmap.c
+++ b/src/soc/intel/baytrail/memmap.c
@@ -13,7 +13,9 @@
* GNU General Public License for more details.
*/
+#include <arch/romstage.h>
#include <cbmem.h>
+#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <soc/iosf.h>
@@ -37,3 +39,16 @@ void smm_region(uintptr_t *start, size_t *size)
*start = (iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20;
*size = smm_region_size();
}
+
+void fill_postcar_frame(struct postcar_frame *pcf)
+{
+ uintptr_t top_of_ram;
+
+ /* Cache at least 8 MiB below the top of ram, and at most 8 MiB
+ * above top of the ram. This satisfies MTRR alignment requirement
+ * with different TSEG size configurations.
+ */
+ top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
+ postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
+ MTRR_TYPE_WRBACK);
+}
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 2b92c32f3a..80915fdca0 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -240,16 +240,3 @@ asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
{
romstage_main(base_timestamp);
}
-
-void fill_postcar_frame(struct postcar_frame *pcf)
-{
- uintptr_t top_of_ram;
-
- /* Cache at least 8 MiB below the top of ram, and at most 8 MiB
- * above top of the ram. This satisfies MTRR alignment requirement
- * with different TSEG size configurations.
- */
- top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
- postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
- MTRR_TYPE_WRBACK);
-}