diff options
Diffstat (limited to 'src/soc/intel/baytrail')
-rw-r--r-- | src/soc/intel/baytrail/acpi.c | 2 | ||||
-rw-r--r-- | src/soc/intel/baytrail/baytrail/gpio.h | 22 | ||||
-rw-r--r-- | src/soc/intel/baytrail/gfx.c | 4 | ||||
-rw-r--r-- | src/soc/intel/baytrail/gpio.c | 16 | ||||
-rw-r--r-- | src/soc/intel/baytrail/hda.c | 6 | ||||
-rw-r--r-- | src/soc/intel/baytrail/iosf.c | 4 | ||||
-rw-r--r-- | src/soc/intel/baytrail/lpe.c | 12 | ||||
-rw-r--r-- | src/soc/intel/baytrail/pmutil.c | 8 | ||||
-rw-r--r-- | src/soc/intel/baytrail/romstage/romstage.c | 10 | ||||
-rw-r--r-- | src/soc/intel/baytrail/sata.c | 2 | ||||
-rw-r--r-- | src/soc/intel/baytrail/smm.c | 2 | ||||
-rw-r--r-- | src/soc/intel/baytrail/southcluster.c | 30 | ||||
-rw-r--r-- | src/soc/intel/baytrail/spi.c | 18 |
13 files changed, 70 insertions, 66 deletions
diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index aae0c9961a..cefc215db2 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -106,7 +106,7 @@ void acpi_init_gnvs(global_nvs_t *gnvs) static int acpi_sci_irq(void) { - const unsigned long actl = ILB_BASE_ADDRESS + ACTL; + u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); int scis; static int sci_irq; diff --git a/src/soc/intel/baytrail/baytrail/gpio.h b/src/soc/intel/baytrail/baytrail/gpio.h index 5071b09b79..d51d6e2983 100644 --- a/src/soc/intel/baytrail/baytrail/gpio.h +++ b/src/soc/intel/baytrail/baytrail/gpio.h @@ -387,15 +387,15 @@ struct soc_gpio_config* mainboard_get_gpios(void); #define PCU_SMB_DATA_PAD 90 #define SOC_DDI1_VDDEN_PAD 16 -static inline unsigned int ncore_pconf0(int pad_num) +static inline u32 *ncore_pconf0(int pad_num) { - return GPNCORE_PAD_BASE + pad_num * 16; + return (u32 *)(GPNCORE_PAD_BASE + pad_num * 16); } static inline void ncore_select_func(int pad, int func) { uint32_t reg; - uint32_t pconf0_addr = ncore_pconf0(pad); + u32 *pconf0_addr = ncore_pconf0(pad); reg = read32(pconf0_addr); reg &= ~0x7; @@ -403,20 +403,20 @@ static inline void ncore_select_func(int pad, int func) write32(pconf0_addr, reg); } -static inline unsigned int score_pconf0(int pad_num) +static inline u32 *score_pconf0(int pad_num) { - return GPSCORE_PAD_BASE + pad_num * 16; + return (u32 *)(GPSCORE_PAD_BASE + pad_num * 16); } -static inline unsigned int ssus_pconf0(int pad_num) +static inline u32 *ssus_pconf0(int pad_num) { - return GPSSUS_PAD_BASE + pad_num * 16; + return (u32 *)(GPSSUS_PAD_BASE + pad_num * 16); } static inline void score_select_func(int pad, int func) { uint32_t reg; - uint32_t pconf0_addr = score_pconf0(pad); + uint32_t *pconf0_addr = score_pconf0(pad); reg = read32(pconf0_addr); reg &= ~0x7; @@ -427,7 +427,7 @@ static inline void score_select_func(int pad, int func) static inline void ssus_select_func(int pad, int func) { uint32_t reg; - uint32_t pconf0_addr = ssus_pconf0(pad); + uint32_t *pconf0_addr = ssus_pconf0(pad); reg = read32(pconf0_addr); reg &= ~0x7; @@ -438,14 +438,14 @@ static inline void ssus_select_func(int pad, int func) /* These functions require that the input pad be configured as an input GPIO */ static inline int score_get_gpio(int pad) { - uint32_t val_addr = score_pconf0(pad) + PAD_VAL_REG; + uint32_t *val_addr = score_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t)); return read32(val_addr) & PAD_VAL_HIGH; } static inline int ssus_get_gpio(int pad) { - uint32_t val_addr = ssus_pconf0(pad) + PAD_VAL_REG; + uint32_t *val_addr = ssus_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t)); return read32(val_addr) & PAD_VAL_HIGH; } diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 4cce87768d..5b57cc3d4f 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -59,7 +59,7 @@ static void gfx_lock_pcbase(device_t dev) pcbase += (gmsize-1) * wopcmsz - pcsize; pcbase |= 1; /* Lock */ - write32(res->base + 0x182120, pcbase); + write32((u32 *)(uintptr_t)(res->base + 0x182120), pcbase); } static const struct reg_script gfx_init_script[] = { @@ -308,7 +308,7 @@ static void set_backlight_pwm(device_t dev, uint32_t bklt_reg, int req_hz) divider = 25 * 1000 * 1000 / (16 * req_hz); /* Do not set duty cycle (lower 16 bits). Just set the divider. */ - write32(res->base + bklt_reg, divider << 16); + write32((u32 *)(uintptr_t)(res->base + bklt_reg), divider << 16); } static void gfx_panel_setup(device_t dev) diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c index 43e52ef9a0..6a971eac76 100644 --- a/src/soc/intel/baytrail/gpio.c +++ b/src/soc/intel/baytrail/gpio.c @@ -142,9 +142,9 @@ static void setup_gpios(const struct soc_gpio_map *gpios, reg, pad_conf0, config->pad_conf1, config->pad_val); #endif - write32(reg + PAD_CONF0_REG, pad_conf0); - write32(reg + PAD_CONF1_REG, config->pad_conf1); - write32(reg + PAD_VAL_REG, config->pad_val); + write32((u32 *)(reg + PAD_CONF0_REG), pad_conf0); + write32((u32 *)(reg + PAD_CONF1_REG), config->pad_conf1); + write32((u32 *)(reg + PAD_VAL_REG), config->pad_val); } if (bank->legacy_base != GP_LEGACY_BASE_NONE) @@ -198,7 +198,7 @@ static void setup_gpio_route(const struct soc_gpio_map *sus, static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS], const struct gpio_bank *bank) { - u32 reg = bank->pad_base + PAD_BASE_DIRQ_OFFSET; + u32 *reg = (u32 *)(bank->pad_base + PAD_BASE_DIRQ_OFFSET); u32 val; int i; @@ -206,10 +206,10 @@ static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS], for (i=0; i<4; ++i) { val = dirq[i * 4 + 3] << 24 | dirq[i * 4 + 2] << 16 | dirq[i * 4 + 1] << 8 | dirq[i * 4]; - write32(reg + i * 4, val); + write32(reg + i, val); #ifdef GPIO_DEBUG printk(BIOS_DEBUG, "Write DIRQ reg(%x) - %x\n", - reg + i * 4, val); + reg + i, val); #endif } } @@ -233,8 +233,8 @@ void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap) */ if (!enable_xdp_tap) { printk(BIOS_DEBUG, "Tri-state TDO and TMS\n"); - write32(GPSSUS_PAD_BASE + 0x2fc, 0xc); - write32(GPSSUS_PAD_BASE + 0x2cc, 0xc); + write32((u32 *)(GPSSUS_PAD_BASE + 0x2fc), 0xc); + write32((u32 *)(GPSSUS_PAD_BASE + 0x2cc), 0xc); } } diff --git a/src/soc/intel/baytrail/hda.c b/src/soc/intel/baytrail/hda.c index c5de654921..010150faad 100644 --- a/src/soc/intel/baytrail/hda.c +++ b/src/soc/intel/baytrail/hda.c @@ -83,6 +83,7 @@ static void hda_init(device_t dev) struct resource *res; int codec_mask; int i; + u8 *base; reg_script_run_on_dev(dev, init_ops); @@ -90,7 +91,8 @@ static void hda_init(device_t dev) if (res == NULL) return; - codec_mask = hda_codec_detect(res->base); + base = res2mmio(res, 0, 0); + codec_mask = hda_codec_detect(base); printk(BIOS_DEBUG, "codec mask = %x\n", codec_mask); if (!codec_mask) @@ -99,7 +101,7 @@ static void hda_init(device_t dev) for (i = 3; i >= 0; i--) { if (!((1 << i) & codec_mask)) continue; - hda_codec_init(res->base, i, sizeof(hdmi_codec_verb_table), + hda_codec_init(base, i, sizeof(hdmi_codec_verb_table), hdmi_codec_verb_table); } } diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index 2b07e2b844..0834f4b088 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -25,11 +25,11 @@ static inline void write_iosf_reg(int reg, uint32_t value) { - write32(IOSF_PCI_BASE + reg, value); + write32((u32 *)(IOSF_PCI_BASE + reg), value); } static inline uint32_t read_iosf_reg(int reg) { - return read32(IOSF_PCI_BASE + reg); + return read32((u32 *)(IOSF_PCI_BASE + reg)); } #else static inline void write_iosf_reg(int reg, uint32_t value) diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index 581f42bfa9..bc467ea3e3 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -90,7 +90,7 @@ static void lpe_enable_acpi_mode(device_t dev) static void setup_codec_clock(device_t dev) { uint32_t reg; - int clk_reg; + u32 *clk_reg; struct soc_intel_baytrail_config *config; const char *freq_str; @@ -119,8 +119,8 @@ static void setup_codec_clock(device_t dev) printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str); - clk_reg = PMC_BASE_ADDRESS + PLT_CLK_CTL_0; - clk_reg += 4 * config->lpe_codec_clk_num; + clk_reg = (u32 *)(PMC_BASE_ADDRESS + PLT_CLK_CTL_0); + clk_reg += config->lpe_codec_clk_num; write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); } @@ -144,8 +144,10 @@ static void lpe_stash_firmware_info(device_t dev) /* C0 and later steppings use an offset in the MMIO space. */ if (pattrs->stepping >= STEP_C0) { mmio = find_resource(dev, PCI_BASE_ADDRESS_0); - write32(mmio->base + FIRMWARE_REG_BASE_C0, res->base); - write32(mmio->base + FIRMWARE_REG_LENGTH_C0, res->size); + write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), + res->base); + write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), + res->size); } } diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index aee37261be..8295b692b7 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -355,10 +355,10 @@ void clear_pmc_status(void) uint32_t prsts; uint32_t gen_pmcon1; - prsts = read32(PMC_BASE_ADDRESS + PRSTS); - gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1); + prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS)); + gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); /* Clear the status bits. The RPS field is cleared on a 0 write. */ - write32(PMC_BASE_ADDRESS + GEN_PMCON1, gen_pmcon1 & ~RPS); - write32(PMC_BASE_ADDRESS + PRSTS, prsts); + write32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS); + write32((u32 *)(PMC_BASE_ADDRESS + PRSTS), prsts); } diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index a989a99c89..91548e3edf 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -84,8 +84,8 @@ static void program_base_addresses(void) static void spi_init(void) { - const unsigned long scs = SPI_BASE_ADDRESS + SCS; - const unsigned long bcr = SPI_BASE_ADDRESS + BCR; + u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS); + u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); uint32_t reg; /* Disable generating SMI when setting WPD bit. */ @@ -169,9 +169,9 @@ static struct chipset_power_state *fill_power_state(void) ps->gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS); ps->gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN); ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); - ps->prsts = read32(PMC_BASE_ADDRESS + PRSTS); - ps->gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1); - ps->gen_pmcon2 = read32(PMC_BASE_ADDRESS + GEN_PMCON2); + ps->prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS)); + ps->gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); + ps->gen_pmcon2 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2)); printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", ps->pm1_sts, ps->pm1_en, ps->pm1_cnt); diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c index 28a2f8cae8..bed57c78a0 100644 --- a/src/soc/intel/baytrail/sata.c +++ b/src/soc/intel/baytrail/sata.c @@ -92,7 +92,7 @@ static void sata_init(struct device *dev) pci_write_config16(dev, 0x92, reg16); if (config->sata_ahci) { - u32 abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); /* Enable CR memory space decoding */ reg16 = pci_read_config16(dev, 0x04); diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index daf759d206..9349dfa056 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -66,7 +66,7 @@ void southcluster_smm_clear_state(void) static void southcluster_smm_route_gpios(void) { - const unsigned long gpio_rout = PMC_BASE_ADDRESS + GPIO_ROUT; + u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT); const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI; uint32_t alt_gpio_reg = 0; uint32_t route_reg = smm_save_params[SMM_SAVE_PARAM_GPIO_ROUTE]; diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 5274b034f2..d0569b45c7 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -134,7 +134,7 @@ static void sc_rtc_init(void) if (ps != NULL) { gen_pmcon1 = ps->gen_pmcon1; } else { - gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1); + gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); } rtc_fail = !!(gen_pmcon1 & RPS); @@ -185,20 +185,20 @@ static void com1_configure_resume(device_t dev) static void sc_init(device_t dev) { int i; - const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; - const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20; - const unsigned long gen_pmcon1 = PMC_BASE_ADDRESS + GEN_PMCON1; - const unsigned long actl = ILB_BASE_ADDRESS + ACTL; + u8 *pr_base = (u8 *)(ILB_BASE_ADDRESS + 0x08); + u16 *ir_base = (u16 *)ILB_BASE_ADDRESS + 0x20; + u32 *gen_pmcon1 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1); + u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); const struct baytrail_irq_route *ir = &global_baytrail_irq_route; struct soc_intel_baytrail_config *config = dev->chip_info; /* Set up the PIRQ PIC routing based on static config. */ for (i = 0; i < NUM_PIRQS; i++) { - write8(pr_base + i*sizeof(ir->pic[i]), ir->pic[i]); + write8(pr_base + i, ir->pic[i]); } /* Set up the per device PIRQ routing base on static config. */ for (i = 0; i < NUM_IR_DEVS; i++) { - write16(ir_base + i*sizeof(ir->pcidev[i]), ir->pcidev[i]); + write16(ir_base + i, ir->pcidev[i]); } /* Route SCI to IRQ9 */ @@ -226,8 +226,8 @@ static void sc_init(device_t dev) /* Set bit in function disable register to hide this device. */ static void sc_disable_devfn(device_t dev) { - const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; - const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; + u32 *func_dis = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS); + u32 *func_dis2 = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS2); uint32_t mask = 0; uint32_t mask2 = 0; @@ -347,7 +347,7 @@ static inline void set_d3hot_bits(device_t dev, int offset) * the audio paths work for LPE audio. */ static void hda_work_around(device_t dev) { - unsigned long gctl = TEMP_BASE_ADDRESS + 0x8; + u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8); /* Need to set magic register 0x43 to 0xd7 in config space. */ pci_write_config8(dev, 0x43, 0xd7); @@ -534,11 +534,11 @@ int __attribute__((weak)) mainboard_get_spi_config(struct spi_config *cfg) static void finalize_chipset(void *unused) { - const unsigned long bcr = SPI_BASE_ADDRESS + BCR; - const unsigned long gcs = RCBA_BASE_ADDRESS + GCS; - const unsigned long gen_pmcon2 = PMC_BASE_ADDRESS + GEN_PMCON2; - const unsigned long etr = PMC_BASE_ADDRESS + ETR; - const unsigned long spi = SPI_BASE_ADDRESS; + u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); + u32 *gcs = (u32 *)(RCBA_BASE_ADDRESS + GCS); + u32 *gen_pmcon2 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2); + u32 *etr = (u32 *)(PMC_BASE_ADDRESS + ETR); + u8 *spi = (u8 *)SPI_BASE_ADDRESS; struct spi_config cfg; /* Set the lock enable on the BIOS control register. */ diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index 8605dfc197..a83fb8e5d4 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -196,33 +196,33 @@ static u32 readl_(const void *addr) static void writeb_(u8 b, const void *addr) { - write8((unsigned long)addr, b); + write8(addr, b); printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", b, ((unsigned) addr & 0xffff) - 0xf020); } static void writew_(u16 b, const void *addr) { - write16((unsigned long)addr, b); + write16(addr, b); printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", b, ((unsigned) addr & 0xffff) - 0xf020); } static void writel_(u32 b, const void *addr) { - write32((unsigned long)addr, b); + write32(addr, b); printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", b, ((unsigned) addr & 0xffff) - 0xf020); } #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ -#define readb_(a) read8((uint32_t)a) -#define readw_(a) read16((uint32_t)a) -#define readl_(a) read32((uint32_t)a) -#define writeb_(val, addr) write8((uint32_t)addr, val) -#define writew_(val, addr) write16((uint32_t)addr, val) -#define writel_(val, addr) write32((uint32_t)addr, val) +#define readb_(a) read8(a) +#define readw_(a) read16(a) +#define readl_(a) read32(a) +#define writeb_(val, addr) write8(addr, val) +#define writew_(val, addr) write16(addr, val) +#define writel_(val, addr) write32(addr, val) #endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ |