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path: root/src/soc/intel/braswell/romstage/romstage.c
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Diffstat (limited to 'src/soc/intel/braswell/romstage/romstage.c')
-rw-r--r--src/soc/intel/braswell/romstage/romstage.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 5fe3550509..e4180641a6 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -161,7 +161,7 @@ int chipset_prev_sleep_state(struct chipset_power_state *ps)
if (ps->pm1_sts & WAK_STS) {
switch (acpi_sleep_from_pm1(ps->pm1_cnt)) {
case ACPI_S3:
- if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
+ if (CONFIG(HAVE_ACPI_RESUME))
prev_sleep_state = ACPI_S3;
break;
case ACPI_S5:
@@ -229,7 +229,7 @@ void soc_memory_init_params(struct romstage_params *params,
config = dev->chip_info;
printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n");
- upd->PcdMrcInitTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
+ upd->PcdMrcInitTsegSize = CONFIG(HAVE_SMI_HANDLER) ?
config->PcdMrcInitTsegSize : 0;
upd->PcdMrcInitMmioSize = config->PcdMrcInitMmioSize;
upd->PcdMrcInitSpdAddr1 = config->PcdMrcInitSpdAddr1;