diff options
Diffstat (limited to 'src/soc/intel/braswell/romstage/uart.c')
-rw-r--r-- | src/soc/intel/braswell/romstage/uart.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/romstage/uart.c b/src/soc/intel/braswell/romstage/uart.c new file mode 100644 index 0000000000..7705746b9e --- /dev/null +++ b/src/soc/intel/braswell/romstage/uart.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <soc/gpio.h> +#include <soc/iomap.h> +#include <soc/lpc.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> + +void byt_config_com1_and_enable(void) +{ + uint32_t reg; + + /* Enable the UART hardware for COM1. */ + reg = 1; + pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); + + /* Set up the pads to select the UART function */ + score_select_func(UART_RXD_PAD, 1); + score_select_func(UART_TXD_PAD, 1); +} |