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-rw-r--r--src/soc/intel/braswell/acpi.c5
-rw-r--r--src/soc/intel/braswell/include/soc/acpi.h1
-rw-r--r--src/soc/intel/braswell/include/soc/nvs.h9
-rw-r--r--src/soc/intel/braswell/lpe.c2
-rw-r--r--src/soc/intel/braswell/lpss.c2
-rw-r--r--src/soc/intel/braswell/ramstage.c8
-rw-r--r--src/soc/intel/braswell/scc.c2
-rw-r--r--src/soc/intel/braswell/smihandler.c6
8 files changed, 16 insertions, 19 deletions
diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index 1290d625ac..98d7980995 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <device/mmio.h>
#include <arch/smp/mpspec.h>
@@ -61,7 +62,7 @@ static acpi_cstate_t cstate_map[] = {
}
};
-void acpi_init_gnvs(global_nvs_t *gnvs)
+void acpi_init_gnvs(struct global_nvs *gnvs)
{
/* Set unknown wake source */
gnvs->pm1i = -1;
@@ -493,7 +494,7 @@ unsigned long southcluster_write_acpi_tables(const struct device *device, unsign
void southcluster_inject_dsdt(const struct device *device)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h
index 5bff07a0fb..cd54f2c066 100644
--- a/src/soc/intel/braswell/include/soc/acpi.h
+++ b/src/soc/intel/braswell/include/soc/acpi.h
@@ -8,7 +8,6 @@
void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
unsigned long acpi_madt_irq_overrides(unsigned long current);
-void acpi_init_gnvs(global_nvs_t *gnvs);
void southcluster_inject_dsdt(const struct device *device);
unsigned long southcluster_write_acpi_tables(const struct device *device,
unsigned long current, struct acpi_rsdp *rsdp);
diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h
index 22ea10fe93..35ab47a1e7 100644
--- a/src/soc/intel/braswell/include/soc/nvs.h
+++ b/src/soc/intel/braswell/include/soc/nvs.h
@@ -7,7 +7,7 @@
#include <soc/device_nvs.h>
#include <vendorcode/google/chromeos/gnvs.h>
-typedef struct global_nvs_t {
+struct __packed global_nvs {
/* Miscellaneous */
u16 osys; /* 0x00 - Operating System */
u8 smif; /* 0x02 - SMI function call ("TRAP") */
@@ -55,11 +55,8 @@ typedef struct global_nvs_t {
/* LPSS (0x1000) */
device_nvs_t dev;
-} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+};
-void acpi_create_gnvs(global_nvs_t *gnvs);
-/* Used in SMM to find the ACPI GNVS address */
-global_nvs_t *smm_get_gnvs(void);
+check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif /* _SOC_NVS_H_ */
diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c
index f3391de443..0fb4ca9bad 100644
--- a/src/soc/intel/braswell/lpe.c
+++ b/src/soc/intel/braswell/lpe.c
@@ -53,7 +53,7 @@ static void lpe_enable_acpi_mode(struct device *dev)
REG_SCRIPT_END
};
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
/* Find ACPI NVS to update BARs */
gnvs = acpi_get_gnvs();
diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c
index 82002487af..d9027f5584 100644
--- a/src/soc/intel/braswell/lpss.c
+++ b/src/soc/intel/braswell/lpss.c
@@ -27,7 +27,7 @@ static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index
REG_SCRIPT_END
};
struct resource *bar;
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
/* Find ACPI NVS to update BARs */
gnvs = acpi_get_gnvs();
diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c
index 893a6b6ea2..eba15274dd 100644
--- a/src/soc/intel/braswell/ramstage.c
+++ b/src/soc/intel/braswell/ramstage.c
@@ -137,16 +137,16 @@ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
static void s3_resume_prepare(void)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
- gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
+ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs));
if (!acpi_is_wakeup_s3() && gnvs)
- memset(gnvs, 0, sizeof(global_nvs_t));
+ memset(gnvs, 0, sizeof(struct global_nvs));
}
static void set_board_id(void)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c
index 0b6385fc24..6f23fda119 100644
--- a/src/soc/intel/braswell/scc.c
+++ b/src/soc/intel/braswell/scc.c
@@ -12,7 +12,7 @@
void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
{
struct resource *bar;
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
printk(BIOS_SPEW, "%s/%s (%s, 0x%08x, 0x%08x)\n",
__FILE__, __func__, dev_name(dev), iosf_reg, nvs_index);
diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c
index 614f56dfdd..28765d0780 100644
--- a/src/soc/intel/braswell/smihandler.c
+++ b/src/soc/intel/braswell/smihandler.c
@@ -19,7 +19,7 @@
#include <smmstore.h>
/* GNVS needs to be set by coreboot initiating a software SMI. */
-static global_nvs_t *gnvs;
+static struct global_nvs *gnvs;
static int smm_initialized;
int southbridge_io_trap_handler(int smif)
@@ -45,7 +45,7 @@ void southbridge_smi_set_eos(void)
enable_smi(EOS);
}
-global_nvs_t *smm_get_gnvs(void)
+struct global_nvs *smm_get_gnvs(void)
{
return gnvs;
}
@@ -307,7 +307,7 @@ static void southbridge_smi_apmc(void)
state = smi_apmc_find_state_save(reg8);
if (state) {
/* EBX in the state save contains the GNVS pointer */
- gnvs = (global_nvs_t *)((uint32_t)state->rbx);
+ gnvs = (struct global_nvs *)((uint32_t)state->rbx);
smm_initialized = 1;
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}