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path: root/src/soc/intel/broadwell/adsp.c
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Diffstat (limited to 'src/soc/intel/broadwell/adsp.c')
-rw-r--r--src/soc/intel/broadwell/adsp.c26
1 files changed, 15 insertions, 11 deletions
diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c
index 9ecbe95b41..bf77763954 100644
--- a/src/soc/intel/broadwell/adsp.c
+++ b/src/soc/intel/broadwell/adsp.c
@@ -69,21 +69,25 @@ static void adsp_init(struct device *dev)
/* Set D3 Power Gating Enable in D19:F0:A0 based on PCH type */
tmp32 = pci_read_config32(dev, ADSP_PCI_VDRTCTL0);
- if (config->adsp_d3_pg_disable) {
- if (pch_is_wpt()) {
- tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT;
- tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT;
+ if (pch_is_wpt()) {
+ if (config->adsp_d3_pg_enable) {
+ tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT;
+ if (config->adsp_sram_pg_enable)
+ tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT;
+ else
+ tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT;
} else {
- tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT;
- tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT;
+ tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT;
}
} else {
- if (pch_is_wpt()) {
- tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT;
- tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT;
- } else {
+ if (config->adsp_d3_pg_enable) {
tmp32 &= ~ADSP_VDRTCTL0_D3PGD_LPT;
- tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT;
+ if (config->adsp_sram_pg_enable)
+ tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT;
+ else
+ tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT;
+ } else {
+ tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT;
}
}
pci_write_config32(dev, ADSP_PCI_VDRTCTL0, tmp32);