diff options
Diffstat (limited to 'src/soc/intel/broadwell/memmap.c')
| -rw-r--r-- | src/soc/intel/broadwell/memmap.c | 19 |
1 files changed, 9 insertions, 10 deletions
diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index 7c53fa6468..f4a9d0ed24 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -16,12 +16,12 @@ #define __SIMPLE_DEVICE__ #include <cbmem.h> +#include <cpu/x86/smm.h> #include <device/pci.h> #include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> #include <soc/smm.h> -#include <stage_cache.h> #include <stdint.h> static uintptr_t dpr_region_start(void) @@ -46,14 +46,13 @@ void *cbmem_top(void) return (void *) dpr_region_start(); } -void stage_cache_external_region(void **base, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - /* The ramstage cache lives in the TSEG region. - * The top of RAM is defined to be the TSEG base address. */ - u32 offset = smm_region_size(); - offset -= CONFIG_IED_REGION_SIZE; - offset -= CONFIG_SMM_RESERVED_SIZE; - - *base = (void *)(cbmem_top() + offset); - *size = CONFIG_SMM_RESERVED_SIZE; + uintptr_t tseg = pci_read_config32(PCI_DEV(0, 0, 0), TSEG); + uintptr_t bgsm = pci_read_config32(PCI_DEV(0, 0, 0), BGSM); + + tseg = ALIGN_DOWN(tseg, 1 * MiB); + bgsm = ALIGN_DOWN(bgsm, 1 * MiB); + *start = tseg; + *size = bgsm - tseg; } |