diff options
Diffstat (limited to 'src/soc/intel/broadwell/romstage')
| -rw-r--r-- | src/soc/intel/broadwell/romstage/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/cpu.c | 6 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/raminit.c | 14 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/report_platform.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/romstage.c | 15 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/uart.c | 85 |
6 files changed, 115 insertions, 7 deletions
diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc index 98d87a4965..f8a961795b 100644 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ b/src/soc/intel/broadwell/romstage/Makefile.inc @@ -10,3 +10,4 @@ romstage-y += smbus.c romstage-y += spi.c romstage-y += stack.c romstage-y += systemagent.c +romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart.c diff --git a/src/soc/intel/broadwell/romstage/cpu.c b/src/soc/intel/broadwell/romstage/cpu.c index e7139b807d..754bc31cd6 100644 --- a/src/soc/intel/broadwell/romstage/cpu.c +++ b/src/soc/intel/broadwell/romstage/cpu.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/cpu.h> #include <stdlib.h> #include <console/console.h> #include <cpu/x86/msr.h> @@ -24,6 +25,11 @@ #include <broadwell/msr.h> #include <broadwell/romstage.h> +u32 cpu_family_model(void) +{ + return cpuid_eax(1) & 0x0fff0ff0; +} + void set_max_freq(void) { msr_t msr, perf_ctl, platform_info; diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 870952f79a..a5f688ea69 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -24,6 +24,7 @@ #include <cbmem.h> #include <console/console.h> #include <device/pci_def.h> +#include <lib.h> #include <string.h> #if CONFIG_EC_GOOGLE_CHROMEEC #include <ec/google/chromeec/ec.h> @@ -73,6 +74,16 @@ void raminit(struct pei_data *pei_data) #endif } + /* + * Do not use saved pei data. Can be set by mainboard romstage + * to force a full train of memory on every boot. + */ + if (pei_data->disable_saved_data) { + printk(BIOS_DEBUG, "Disabling PEI saved data by request\n"); + pei_data->saved_data = NULL; + pei_data->saved_data_size = 0; + } + /* Determine if mrc.bin is in the cbfs. */ entry = (pei_wrapper_entry_t)cbfs_get_file_content( CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab); @@ -95,6 +106,9 @@ void raminit(struct pei_data *pei_data) report_memory_config(); + /* Basic memory sanity test */ + quick_ram_check(); + if (pei_data->boot_mode != SLEEP_STATE_S3) { cbmem_initialize_empty(); } else if (cbmem_initialize()) { diff --git a/src/soc/intel/broadwell/romstage/report_platform.c b/src/soc/intel/broadwell/romstage/report_platform.c index 3c4016fa1f..4e161dc442 100644 --- a/src/soc/intel/broadwell/romstage/report_platform.c +++ b/src/soc/intel/broadwell/romstage/report_platform.c @@ -41,6 +41,7 @@ static struct { { CPUID_HASWELL_HALO, "Haswell Perf Halo" }, { CPUID_BROADWELL_C0, "Broadwell C0" }, { CPUID_BROADWELL_D0, "Broadwell D0" }, + { CPUID_BROADWELL_E0, "Broadwell E0" }, }; static struct { diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 84d1f11f5c..1d5ee89d54 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -73,6 +73,9 @@ void * asmlinkage romstage_main(unsigned long bist, /* Start console drivers */ console_init(); + /* Get power state */ + rp.power_state = fill_power_state(); + /* Print useful platform information */ report_platform_info(); @@ -96,19 +99,16 @@ static inline void chromeos_init(int prev_sleep_state) /* Entry from the mainboard. */ void romstage_common(struct romstage_params *params) { - struct chipset_power_state *ps; struct romstage_handoff *handoff; post_code(0x32); mark_ts(params, timestamp_get()); - /* Get power state */ - ps = fill_power_state(); - params->pei_data->boot_mode = ps->prev_sleep_state; + params->pei_data->boot_mode = params->power_state->prev_sleep_state; #if CONFIG_ELOG_BOOT_COUNT - if (ps->prev_sleep_state != SLEEP_STATE_S3) + if (params->power_state->prev_sleep_state != SLEEP_STATE_S3) boot_count_increment(); #endif @@ -121,11 +121,12 @@ void romstage_common(struct romstage_params *params) handoff = romstage_handoff_find_or_add(); if (handoff != NULL) - handoff->s3_resume = (ps->prev_sleep_state == SLEEP_STATE_S3); + handoff->s3_resume = (params->power_state->prev_sleep_state == + SLEEP_STATE_S3); else printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - chromeos_init(ps->prev_sleep_state); + chromeos_init(params->power_state->prev_sleep_state); /* Save timestamp information. */ timestamp_init(params->ts.times[0]); diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c new file mode 100644 index 0000000000..8214a8a116 --- /dev/null +++ b/src/soc/intel/broadwell/romstage/uart.c @@ -0,0 +1,85 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/early_variables.h> +#include <arch/io.h> +#include <delay.h> +#include <device/pci_def.h> +#include <reg_script.h> +#include <stdint.h> +#include <uart8250.h> +#include <broadwell/iobp.h> +#include <broadwell/serialio.h> + +const struct reg_script uart_init[] = { + /* Set MMIO BAR */ + REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, CONFIG_TTYS0_BASE), + /* Enable Memory access and Bus Master */ + REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER), + /* Initialize LTR */ + REG_MMIO_RMW32(CONFIG_TTYS0_BASE + SIO_REG_PPR_GEN, + ~SIO_REG_PPR_GEN_LTR_MODE_MASK, 0), + REG_MMIO_RMW32(CONFIG_TTYS0_BASE + SIO_REG_PPR_RST, + ~(SIO_REG_PPR_RST_ASSERT), 0), + /* Take UART out of reset */ + REG_MMIO_OR32(CONFIG_TTYS0_BASE + SIO_REG_PPR_RST, + SIO_REG_PPR_RST_ASSERT), + /* Set M and N divisor inputs and enable clock */ + REG_MMIO_WRITE32(CONFIG_TTYS0_BASE + SIO_REG_PPR_CLOCK, + SIO_REG_PPR_CLOCK_EN | SIO_REG_PPR_CLOCK_UPDATE | + (SIO_REG_PPR_CLOCK_N_DIV << 16) | + (SIO_REG_PPR_CLOCK_M_DIV << 1)), + REG_SCRIPT_END +}; + +void pch_uart_init(void) +{ + /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */ + u32 gpiodf = 0x131f; + device_t dev; + + /* Put UART in byte access mode for 16550 compatibility */ + switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) { + case 0: + dev = PCH_DEV_UART0; + gpiodf |= SIO_IOBP_GPIODF_UART0_BYTE_ACCESS; + break; + case 1: + dev = PCH_DEV_UART1; + gpiodf |= SIO_IOBP_GPIODF_UART1_BYTE_ACCESS; + break; + default: + return; + } + + /* Program IOBP GPIODF */ + pch_iobp_update(SIO_IOBP_GPIODF, ~gpiodf, gpiodf); + + /* Program IOBP CB000180h[5:0] = 111111b (undefined register) */ + pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f); + + /* Initialize chipset uart interface */ + reg_script_run_on_dev(dev, uart_init); + + /* + * Perform standard UART initialization + * Divisor 1 is 115200 BAUD + */ + uart8250_mem_init(CONFIG_TTYS0_BASE, 1); +} |