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-rw-r--r--src/soc/intel/broadwell/acpi.c6
-rw-r--r--src/soc/intel/broadwell/chip.c2
-rw-r--r--src/soc/intel/broadwell/finalize.c2
-rw-r--r--src/soc/intel/broadwell/igd.c2
-rw-r--r--src/soc/intel/broadwell/include/soc/ramstage.h2
-rw-r--r--src/soc/intel/broadwell/lpc.c6
-rw-r--r--src/soc/intel/broadwell/me.c14
-rw-r--r--src/soc/intel/broadwell/pcie.c4
-rw-r--r--src/soc/intel/broadwell/romstage/power_state.c2
-rw-r--r--src/soc/intel/broadwell/romstage/raminit.c6
-rw-r--r--src/soc/intel/broadwell/romstage/romstage.c2
-rw-r--r--src/soc/intel/broadwell/serialio.c4
-rw-r--r--src/soc/intel/broadwell/smihandler.c10
-rw-r--r--src/soc/intel/broadwell/spi.c2
-rw-r--r--src/soc/intel/broadwell/systemagent.c2
15 files changed, 33 insertions, 33 deletions
diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c
index aa2dd2ad8e..e51c9bf7ce 100644
--- a/src/soc/intel/broadwell/acpi.c
+++ b/src/soc/intel/broadwell/acpi.c
@@ -169,15 +169,15 @@ void acpi_init_gnvs(global_nvs_t *gnvs)
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
-#if IS_ENABLED(CONFIG_CONSOLE_CBMEM)
+#if CONFIG(CONSOLE_CBMEM)
/* Update the mem console pointer. */
gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
#endif
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
/* Initialize Verified Boot data */
chromeos_init_chromeos_acpi(&(gnvs->chromeos));
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif
diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c
index aab8045f3f..6383e15e79 100644
--- a/src/soc/intel/broadwell/chip.c
+++ b/src/soc/intel/broadwell/chip.c
@@ -30,7 +30,7 @@ static struct device_operations pci_domain_ops = {
.read_resources = &pci_domain_read_resources,
.set_resources = &pci_domain_set_resources,
.scan_bus = &pci_domain_scan_bus,
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
.write_acpi_tables = &northbridge_write_acpi_tables,
#endif
};
diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c
index 964534831d..1adbbc8aa2 100644
--- a/src/soc/intel/broadwell/finalize.c
+++ b/src/soc/intel/broadwell/finalize.c
@@ -56,7 +56,7 @@ const struct reg_script system_agent_finalize_script[] = {
};
const struct reg_script pch_finalize_script[] = {
-#if !IS_ENABLED(CONFIG_SPI_CONSOLE)
+#if !CONFIG(SPI_CONSOLE)
/* Set SPI opcode menu */
REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_PREOP,
SPI_OPPREFIX),
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index 94ec3a72f8..319549df1e 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -512,7 +512,7 @@ static void igd_init(struct device *dev)
/* Wait for any configured pre-graphics delay */
if (!acpi_is_wakeup_s3()) {
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
if (display_init_required() || vboot_wants_oprom())
mdelay(CONFIG_PRE_GRAPHICS_DELAY);
#else
diff --git a/src/soc/intel/broadwell/include/soc/ramstage.h b/src/soc/intel/broadwell/include/soc/ramstage.h
index 7292bcf386..71c7999e5b 100644
--- a/src/soc/intel/broadwell/include/soc/ramstage.h
+++ b/src/soc/intel/broadwell/include/soc/ramstage.h
@@ -23,7 +23,7 @@ void broadwell_init_pre_device(void *chip_info);
void broadwell_init_cpus(struct device *dev);
void broadwell_pch_enable_dev(struct device *dev);
-#if IS_ENABLED(CONFIG_HAVE_REFCODE_BLOB)
+#if CONFIG(HAVE_REFCODE_BLOB)
void broadwell_run_reference_code(void);
#else
static inline void broadwell_run_reference_code(void) { }
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 63db9aaafc..c831c2c5bc 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -219,7 +219,7 @@ static const struct reg_script pch_misc_init_script[] = {
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1114, (1 << 15) | (1 << 14)),
/* Setup SERIRQ, enable continuous mode */
REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)),
-#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
+#if !CONFIG(SERIRQ_CONTINUOUS_MODE)
REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0),
#endif
REG_SCRIPT_END
@@ -429,7 +429,7 @@ static void pch_cg_init(struct device *dev)
static void pch_set_acpi_mode(void)
{
-#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+#if CONFIG(HAVE_SMI_HANDLER)
if (!acpi_is_wakeup_s3()) {
printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_DISABLE, APM_CNT);
@@ -621,7 +621,7 @@ static unsigned long broadwell_write_acpi_tables(struct device *device,
unsigned long current,
struct acpi_rsdp *rsdp)
{
- if (IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE))
+ if (CONFIG(INTEL_PCH_UART_CONSOLE))
current = acpi_write_dbg2_pci_uart(rsdp, current,
(CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 1) ?
PCH_DEV_UART1 : PCH_DEV_UART0,
diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c
index 73317e3e71..dd5e5b870c 100644
--- a/src/soc/intel/broadwell/me.c
+++ b/src/soc/intel/broadwell/me.c
@@ -40,7 +40,7 @@
#include <soc/rcba.h>
#include <soc/intel/broadwell/chip.h>
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
#include <vendorcode/google/chromeos/chromeos.h>
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@@ -58,7 +58,7 @@ static const char *me_bios_path_values[] = {
/* MMIO base address for MEI interface */
static u8 *mei_base_address;
-#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
+#if CONFIG(DEBUG_INTEL_ME)
static void mei_dump(void *ptr, int dword, int offset, const char *type)
{
struct mei_csr *csr;
@@ -483,7 +483,7 @@ static void me_print_fw_version(mbp_fw_version_name *vers_name)
vers_name->hotfix_version, vers_name->build_version);
}
-#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
+#if CONFIG(DEBUG_INTEL_ME)
static inline void print_cap(const char *name, int state)
{
printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n",
@@ -703,7 +703,7 @@ static me_bios_path intel_me_path(struct device *dev)
path = ME_ERROR_BIOS_PATH;
}
-#if IS_ENABLED(CONFIG_ELOG)
+#if CONFIG(ELOG)
if (path != ME_NORMAL_BIOS_PATH) {
struct elog_event_data_me_extended data = {
.current_working_state = hfs.working_state,
@@ -792,7 +792,7 @@ static int intel_me_extend_valid(struct device *dev)
}
printk(BIOS_DEBUG, "\n");
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
/* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count);
#endif
@@ -804,7 +804,7 @@ static void intel_me_print_mbp(me_bios_payload *mbp_data)
{
me_print_fw_version(mbp_data->fw_version_name);
-#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
+#if CONFIG(DEBUG_INTEL_ME)
me_print_fwcaps(mbp_data->fw_capabilities);
#endif
@@ -912,7 +912,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev)
}
/* Dump out the MBP contents. */
-#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
+#if CONFIG(DEBUG_INTEL_ME)
printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n",
mbp->header.num_entries, mbp->header.mbp_size);
for (i = 0; i < mbp->header.mbp_size - 1; i++)
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index 3fd5ea4f10..32135eedbb 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -555,7 +555,7 @@ static void pch_pcie_early(struct device *dev)
pci_update_config8(dev, 0xf5, 0x0f, 0);
/* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */
- if (IS_ENABLED(CONFIG_PCIEXP_AER))
+ if (CONFIG(PCIEXP_AER))
pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff,
(1 << 29) | 0x10001);
else
@@ -563,7 +563,7 @@ static void pch_pcie_early(struct device *dev)
(1 << 29));
/* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */
- if (IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE))
+ if (CONFIG(PCIEXP_L1_SUB_STATE))
pci_update_config32(dev, 0x200, ~0xfffff, 0x001e);
else
pci_update_config32(dev, 0x200, ~0xfffff, 0);
diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/romstage/power_state.c
index 291d5eb9ea..ca22b4ef5b 100644
--- a/src/soc/intel/broadwell/romstage/power_state.c
+++ b/src/soc/intel/broadwell/romstage/power_state.c
@@ -57,7 +57,7 @@ static int prev_sleep_state(struct chipset_power_state *ps)
if (ps->pm1_sts & WAK_STS) {
switch (acpi_sleep_from_pm1(ps->pm1_cnt)) {
case ACPI_S3:
- if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
+ if (CONFIG(HAVE_ACPI_RESUME))
prev_sleep_state = ACPI_S3;
break;
case ACPI_S5:
diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c
index acb435bce0..04657aebd8 100644
--- a/src/soc/intel/broadwell/romstage/raminit.c
+++ b/src/soc/intel/broadwell/romstage/raminit.c
@@ -24,7 +24,7 @@
#include <memory_info.h>
#include <mrc_cache.h>
#include <string.h>
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
#endif
@@ -57,7 +57,7 @@ void raminit(struct pei_data *pei_data)
pei_data->saved_data_size = region_device_sz(&rdev);
pei_data->saved_data = rdev_mmap_full(&rdev);
/* Assume boot device is memory mapped. */
- assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED));
+ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
} else if (pei_data->boot_mode == ACPI_S3) {
/* Waking from S3 and no cache. */
printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n");
@@ -104,7 +104,7 @@ void raminit(struct pei_data *pei_data)
if (pei_data->boot_mode != ACPI_S3) {
cbmem_initialize_empty();
} else if (cbmem_initialize()) {
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#if CONFIG(HAVE_ACPI_RESUME)
printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
/* Failed S3 resume, reset to come up cleanly */
system_reset();
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 9aa31b85c1..2531665f1f 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -123,7 +123,7 @@ void romstage_common(struct romstage_params *params)
params->pei_data->boot_mode = params->power_state->prev_sleep_state;
-#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
+#if CONFIG(ELOG_BOOT_COUNT)
if (params->power_state->prev_sleep_state != ACPI_S3)
boot_count_increment();
#endif
diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c
index 0330acb91b..59fb4f7a7e 100644
--- a/src/soc/intel/broadwell/serialio.c
+++ b/src/soc/intel/broadwell/serialio.c
@@ -41,7 +41,7 @@ static void serialio_enable_d3hot(struct resource *res)
static int serialio_uart_is_debug(struct device *dev)
{
-#if IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE)
+#if CONFIG(INTEL_PCH_UART_CONSOLE)
switch (dev->path.pci.devfn) {
case PCH_DEVFN_UART0: /* UART0 */
return !!(CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 0);
@@ -278,7 +278,7 @@ static void serialio_set_resources(struct device *dev)
{
pci_dev_set_resources(dev);
-#if IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE)
+#if CONFIG(INTEL_PCH_UART_CONSOLE)
/* Update UART base address if used for debug */
if (serialio_uart_is_debug(dev)) {
struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c
index 9f5d81dc31..b36b99dd4e 100644
--- a/src/soc/intel/broadwell/smihandler.c
+++ b/src/soc/intel/broadwell/smihandler.c
@@ -178,7 +178,7 @@ static void southbridge_smi_sleep(void)
/* USB sleep preparations */
usb_xhci_sleep_prepare(PCH_DEV_XHCI, slp_typ);
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
/* Log S3, S4, and S5 entry */
if (slp_typ >= ACPI_S3)
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
@@ -292,7 +292,7 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
return NULL;
}
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
static void southbridge_smi_gsmi(void)
{
u32 *ret, *param;
@@ -325,7 +325,7 @@ static void finalize(void)
}
finalize_done = 1;
-#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
+#if CONFIG(SPI_FLASH_SMM)
/* Re-init SPI driver to handle locked BAR */
spi_init();
#endif
@@ -371,7 +371,7 @@ static void southbridge_smi_apmc(void)
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
break;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
case APM_CNT_ELOG_GSMI:
southbridge_smi_gsmi();
break;
@@ -390,7 +390,7 @@ static void southbridge_smi_pm1(void)
*/
if (pm1_sts & PWRBTN_STS) {
/* power button pressed */
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
elog_add_event(ELOG_TYPE_POWER_BUTTON);
#endif
disable_pm1_control(-1UL);
diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c
index 21417cf828..d8127577db 100644
--- a/src/soc/intel/broadwell/spi.c
+++ b/src/soc/intel/broadwell/spi.c
@@ -133,7 +133,7 @@ enum {
SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3
};
-#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
+#if CONFIG(DEBUG_SPI_FLASH)
static u8 readb_(const void *addr)
{
diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c
index 3912688181..aef1d1cd44 100644
--- a/src/soc/intel/broadwell/systemagent.c
+++ b/src/soc/intel/broadwell/systemagent.c
@@ -384,7 +384,7 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
reserved_ram_resource(dev, index++, (0xc0000 >> 10),
(0x100000 - 0xc0000) >> 10);
- if (IS_ENABLED(CONFIG_CHROMEOS))
+ if (CONFIG(CHROMEOS))
chromeos_reserve_ram_oops(dev, index++);
*resource_cnt = index;
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-02 13:53:20 +0000