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-rw-r--r--src/soc/intel/broadwell/finalize.c4
-rw-r--r--src/soc/intel/broadwell/include/soc/pci_devs.h15
-rw-r--r--src/soc/intel/broadwell/lpc.c3
-rw-r--r--src/soc/intel/broadwell/smmrelocate.c3
-rw-r--r--src/soc/intel/broadwell/systemagent.c12
5 files changed, 21 insertions, 16 deletions
diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c
index 1adbbc8aa2..06cc18d67a 100644
--- a/src/soc/intel/broadwell/finalize.c
+++ b/src/soc/intel/broadwell/finalize.c
@@ -96,9 +96,11 @@ const struct reg_script pch_finalize_script[] = {
static void broadwell_finalize(void *unused)
{
+ struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
+
printk(BIOS_DEBUG, "Finalizing chipset.\n");
- reg_script_run_on_dev(SA_DEV_ROOT, system_agent_finalize_script);
+ reg_script_run_on_dev(sa_dev, system_agent_finalize_script);
reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script);
/* Lock */
diff --git a/src/soc/intel/broadwell/include/soc/pci_devs.h b/src/soc/intel/broadwell/include/soc/pci_devs.h
index ae3e08f661..7ab54141e5 100644
--- a/src/soc/intel/broadwell/include/soc/pci_devs.h
+++ b/src/soc/intel/broadwell/include/soc/pci_devs.h
@@ -16,32 +16,29 @@
#ifndef _BROADWELL_PCI_DEVS_H_
#define _BROADWELL_PCI_DEVS_H_
-#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
#if defined(__SIMPLE_DEVICE__)
-#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
#else
#include <device/device.h>
#include <device/pci_def.h>
-#define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__)
#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__)
#endif
/* System Agent Devices */
#define SA_DEV_SLOT_ROOT 0x00
-#define SA_DEVFN_ROOT _SA_DEVFN(ROOT)
-#define SA_DEV_ROOT _SA_DEV(ROOT)
+#define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0)
+#define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0)
#define SA_DEV_SLOT_IGD 0x02
-#define SA_DEVFN_IGD _SA_DEVFN(IGD)
-#define SA_DEV_IGD _SA_DEV(IGD)
+#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0)
+#define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0)
#define SA_DEV_SLOT_MINIHD 0x03
-#define SA_DEVFN_MINIHD _SA_DEVFN(MINIHD)
-#define SA_DEV_MINIHD _SA_DEV(MINIHD)
+#define SA_DEVFN_MINIHD PCI_DEVFN(SA_DEV_SLOT_MINIHD, 0)
+#define SA_DEV_MINIHD PCI_DEV(0, SA_DEV_SLOT_MINIHD, 0)
/* PCH Devices */
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 9be4aebdd2..b385d6b637 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -365,6 +365,7 @@ static void pch_cg_init(struct device *dev)
{
u32 reg32;
u16 reg16;
+ struct device *igd_dev = pcidev_path_on_root(SA_DEVFN_IGD);
/* DMI */
RCBA32_OR(0x2234, 0xf);
@@ -388,7 +389,7 @@ static void pch_cg_init(struct device *dev)
RCBA32_AND_OR(0x2614, ~0x64ff0000, 0x0a206500);
/* Check for 0:2.0@0x08 >= 0x0b */
- if (pch_is_wpt() || pci_read_config8(SA_DEV_IGD, 0x8) >= 0x0b)
+ if (pch_is_wpt() || pci_read_config8(igd_dev, 0x8) >= 0x0b)
RCBA32_OR(0x2614, (1 << 26));
RCBA32_OR(0x900, 0x0000031f);
diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c
index 98c3c4cddd..9ea73b2054 100644
--- a/src/soc/intel/broadwell/smmrelocate.c
+++ b/src/soc/intel/broadwell/smmrelocate.c
@@ -319,10 +319,11 @@ void smm_relocate(void)
void smm_lock(void)
{
+ struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
/* LOCK the SMM memory window and enable normal SMM.
* After running this function, only a full reset can
* make the SMM registers writable again.
*/
printk(BIOS_DEBUG, "Locking SMM.\n");
- pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
+ pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
}
diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c
index c6444b15e8..b6b5608a24 100644
--- a/src/soc/intel/broadwell/systemagent.c
+++ b/src/soc/intel/broadwell/systemagent.c
@@ -32,19 +32,22 @@
u8 systemagent_revision(void)
{
- return pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID);
+ struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
+ return pci_read_config8(sa_dev, PCI_REVISION_ID);
}
uintptr_t sa_get_tolud_base(void)
{
+ struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
/* Bit 0 is lock bit, not part of address */
- return pci_read_config32(SA_DEV_ROOT, TOLUD) & ~1;
+ return pci_read_config32(sa_dev, TOLUD) & ~1;
}
uintptr_t sa_get_gsm_base(void)
{
+ struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
/* Bit 0 is lock bit, not part of address */
- return pci_read_config32(SA_DEV_ROOT, BGSM) & ~1;
+ return pci_read_config32(sa_dev, BGSM) & ~1;
}
static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base,
@@ -291,6 +294,7 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
uint64_t mc_values[NUM_MAP_ENTRIES];
unsigned long dpr_size = 0;
u32 dpr_reg;
+ struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
/* Read in the MAP registers and report their values. */
mc_read_map_entries(dev, &mc_values[0]);
@@ -302,7 +306,7 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
* the DPR register reports the TOP of the region, which is the same
* as TSEG base. The region size is reported in MiB in bits 11:4.
*/
- dpr_reg = pci_read_config32(SA_DEV_ROOT, DPR);
+ dpr_reg = pci_read_config32(sa_dev, DPR);
if (dpr_reg & DPR_EPM) {
dpr_size = (dpr_reg & DPR_SIZE_MASK) << 16;
printk(BIOS_INFO, "DPR SIZE: 0x%lx\n", dpr_size);