diff options
Diffstat (limited to 'src/soc/intel/broadwell')
| -rw-r--r-- | src/soc/intel/broadwell/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/cpu.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/cache_as_ram.inc | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/stack.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/smmrelocate.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/stage_cache.c | 2 |
6 files changed, 7 insertions, 7 deletions
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 545eb62058..2d6176af6b 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -109,7 +109,7 @@ config DCACHE_RAM_ROMSTAGE_STACK_SIZE default 0x2000 help The amount of anticipated stack usage from the data cache - during pre-ram rom stage execution. + during pre-ram ROM stage execution. config HAVE_MRC bool "Add a Memory Reference Code binary" diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 2afdfadc3e..16f350c993 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -576,7 +576,7 @@ static void cpu_core_init(device_t cpu) /* Clear out pending MCEs */ configure_mca(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ enable_lapic_tpr(); setup_lapic(); diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc index 37d7f30a68..24720d14a3 100644 --- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc +++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc @@ -147,7 +147,7 @@ clear_mtrrs: wrmsr post_code(0x27) - /* Enable caching for ram init code to run faster */ + /* Enable caching for RAM init code to run faster */ movl $MTRR_PHYS_BASE(2), %ecx movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx diff --git a/src/soc/intel/broadwell/romstage/stack.c b/src/soc/intel/broadwell/romstage/stack.c index 76307cfbb5..86a1c02b15 100644 --- a/src/soc/intel/broadwell/romstage/stack.c +++ b/src/soc/intel/broadwell/romstage/stack.c @@ -78,7 +78,7 @@ void *setup_stack_and_mttrs(void) num_mtrrs++; top_of_ram = (uint32_t)cbmem_top(); - /* Cache 8MiB below the top of ram. The top of ram under 4GiB is the + /* Cache 8MiB below the top of ram. The top of RAM under 4GiB is the * start of the TSEG region. It is required to be 8MiB aligned. Set * this area as cacheable so it can be used later for ramstage before * setting up the entire RAM as cacheable. */ @@ -88,7 +88,7 @@ void *setup_stack_and_mttrs(void) slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK); num_mtrrs++; - /* Cache 8MiB at the top of ram. Top of ram is where the TSEG + /* Cache 8MiB at the top of ram. Top of RAM is where the TSEG * region resides. However, it is not restricted to SMM mode until * SMM has been relocated. By setting the region to cacheable it * provides faster access when relocating the SMM handler as well diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index 6fd609b508..873e909c85 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -136,7 +136,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, msr_t mtrr_cap; struct smm_relocation_params *relo_params = &smm_reloc_params; - printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); + printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu); /* Determine if the processor supports saving state in MSRs. If so, * enable it before the non-BSPs run so that SMM relocation can occur diff --git a/src/soc/intel/broadwell/stage_cache.c b/src/soc/intel/broadwell/stage_cache.c index 03c63575d0..dc59ab7756 100644 --- a/src/soc/intel/broadwell/stage_cache.c +++ b/src/soc/intel/broadwell/stage_cache.c @@ -21,7 +21,7 @@ void stage_cache_external_region(void **base, size_t *size) { /* The ramstage cache lives in the TSEG region. - * The top of ram is defined to be the TSEG base address. */ + * The top of RAM is defined to be the TSEG base address. */ u32 offset = smm_region_size(); offset -= CONFIG_IED_REGION_SIZE; offset -= CONFIG_SMM_RESERVED_SIZE; |