diff options
Diffstat (limited to 'src/soc/intel/broadwell')
| -rw-r--r-- | src/soc/intel/broadwell/acpi.c | 6 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/include/soc/ramstage.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/lpc.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/me.c | 14 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/raminit.c | 6 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/romstage.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/serialio.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/smihandler.c | 10 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/spi.c | 2 |
9 files changed, 26 insertions, 26 deletions
diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 6d20259c13..a23c8e2f4d 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -169,15 +169,15 @@ void acpi_init_gnvs(global_nvs_t *gnvs) /* CPU core count */ gnvs->pcnt = dev_count_cpu(); -#if CONFIG_CONSOLE_CBMEM +#if IS_ENABLED(CONFIG_CONSOLE_CBMEM) /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); #endif -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Initialize Verified Boot data */ chromeos_init_vboot(&(gnvs->chromeos)); -#if CONFIG_EC_GOOGLE_CHROMEEC +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif diff --git a/src/soc/intel/broadwell/include/soc/ramstage.h b/src/soc/intel/broadwell/include/soc/ramstage.h index db67fe3502..1009bbaf69 100644 --- a/src/soc/intel/broadwell/include/soc/ramstage.h +++ b/src/soc/intel/broadwell/include/soc/ramstage.h @@ -23,7 +23,7 @@ void broadwell_init_pre_device(void *chip_info); void broadwell_init_cpus(device_t dev); void broadwell_pch_enable_dev(device_t dev); -#if CONFIG_HAVE_REFCODE_BLOB +#if IS_ENABLED(CONFIG_HAVE_REFCODE_BLOB) void broadwell_run_reference_code(void); #else static inline void broadwell_run_reference_code(void) { } diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 36e34fe3fc..4430e73b46 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -221,7 +221,7 @@ static const struct reg_script pch_misc_init_script[] = { REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1114, (1 << 15) | (1 << 14)), /* Setup SERIRQ, enable continuous mode */ REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)), -#if !CONFIG_SERIRQ_CONTINUOUS_MODE +#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0), #endif REG_SCRIPT_END @@ -431,7 +431,7 @@ static void pch_cg_init(device_t dev) static void pch_set_acpi_mode(void) { -#if CONFIG_HAVE_SMI_HANDLER +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) if (!acpi_is_wakeup_s3()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 73b3c2e63c..ed2f7283d3 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -39,7 +39,7 @@ #include <soc/rcba.h> #include <soc/intel/broadwell/chip.h> -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -57,7 +57,7 @@ static const char *me_bios_path_values[] = { /* MMIO base address for MEI interface */ static u8 *mei_base_address; -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -482,7 +482,7 @@ static void me_print_fw_version(mbp_fw_version_name *vers_name) vers_name->hotfix_version, vers_name->build_version); } -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", @@ -702,7 +702,7 @@ static me_bios_path intel_me_path(device_t dev) path = ME_ERROR_BIOS_PATH; } -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -791,7 +791,7 @@ static int intel_me_extend_valid(device_t dev) } printk(BIOS_DEBUG, "\n"); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif @@ -803,7 +803,7 @@ static void intel_me_print_mbp(me_bios_payload *mbp_data) { me_print_fw_version(mbp_data->fw_version_name); -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) me_print_fwcaps(mbp_data->fw_capabilities); #endif @@ -911,7 +911,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev) } /* Dump out the MBP contents. */ -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", mbp->header.num_entries, mbp->header.mbp_size); for (i = 0; i < mbp->header.mbp_size - 1; i++) diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 10cb733e52..34ab39cad7 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -22,7 +22,7 @@ #include <device/pci_def.h> #include <lib.h> #include <string.h> -#if CONFIG_EC_GOOGLE_CHROMEEC +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> #endif @@ -65,7 +65,7 @@ void raminit(struct pei_data *pei_data) reset_system(); } else { printk(BIOS_DEBUG, "No MRC cache found.\n"); -#if CONFIG_EC_GOOGLE_CHROMEEC +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) if (pei_data->boot_mode == ACPI_S0) { /* Ensure EC is running RO firmware. */ google_chromeec_check_ec_image(EC_IMAGE_RO); @@ -110,7 +110,7 @@ void raminit(struct pei_data *pei_data) if (pei_data->boot_mode != ACPI_S3) { cbmem_initialize_empty(); } else if (cbmem_initialize()) { -#if CONFIG_HAVE_ACPI_RESUME +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ reset_system(); diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index af95530c77..b5e52292a4 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -91,7 +91,7 @@ void romstage_common(struct romstage_params *params) params->pei_data->boot_mode = params->power_state->prev_sleep_state; -#if CONFIG_ELOG_BOOT_COUNT +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) if (params->power_state->prev_sleep_state != ACPI_S3) boot_count_increment(); #endif @@ -110,7 +110,7 @@ void romstage_common(struct romstage_params *params) romstage_handoff_init(params->power_state->prev_sleep_state == ACPI_S3); -#if CONFIG_LPC_TPM +#if IS_ENABLED(CONFIG_LPC_TPM) init_tpm(params->power_state->prev_sleep_state == ACPI_S3); #endif } diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index a73312c6af..eb70112072 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -40,7 +40,7 @@ static void serialio_enable_d3hot(struct resource *res) static int serialio_uart_is_debug(struct device *dev) { -#if CONFIG_INTEL_PCH_UART_CONSOLE +#if IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE) switch (dev->path.pci.devfn) { case PCH_DEVFN_UART0: /* UART0 */ return !!(CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 0); @@ -277,7 +277,7 @@ static void serialio_set_resources(struct device *dev) { pci_dev_set_resources(dev); -#if CONFIG_INTEL_PCH_UART_CONSOLE +#if IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE) /* Update UART base address if used for debug */ if (serialio_uart_is_debug(dev)) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 8a5b443ac8..0b8a970689 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -176,7 +176,7 @@ static void southbridge_smi_sleep(void) /* USB sleep preparations */ usb_xhci_sleep_prepare(PCH_DEV_XHCI, slp_typ); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -290,7 +290,7 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) return NULL; } -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -323,7 +323,7 @@ static void finalize(void) } finalize_done = 1; -#if CONFIG_SPI_FLASH_SMM +#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) /* Re-init SPI driver to handle locked BAR */ spi_init(); #endif @@ -369,7 +369,7 @@ static void southbridge_smi_apmc(void) printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) case ELOG_GSMI_APM_CNT: southbridge_smi_gsmi(); break; @@ -388,7 +388,7 @@ static void southbridge_smi_pm1(void) */ if (pm1_sts & PWRBTN_STS) { /* power button pressed */ -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif disable_pm1_control(-1UL); diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index eea3ade7f5..3ebc3bfaca 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -162,7 +162,7 @@ enum { SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 }; -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) static u8 readb_(const void *addr) { |