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Diffstat (limited to 'src/soc/intel/cannonlake/chip.c')
-rw-r--r--src/soc/intel/cannonlake/chip.c19
1 files changed, 2 insertions, 17 deletions
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 0ce2f1aca7..2bb1c92612 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -23,6 +23,7 @@
#include <intelblocks/xdci.h>
#include <romstage_handoff.h>
#include <soc/intel/common/vbt.h>
+#include <soc/gpio.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
@@ -166,22 +167,6 @@ void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads)
gpio_configure_pads(cfg, num_pads);
}
-/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */
-static void soc_fill_gpio_pm_configuration(void)
-{
- uint8_t value[TOTAL_GPIO_COMM];
- const config_t *config = config_of_soc();
-
- if (config->gpio_override_pm)
- memcpy(value, config->gpio_pm, sizeof(uint8_t) *
- TOTAL_GPIO_COMM);
- else
- memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) *
- TOTAL_GPIO_COMM);
-
- gpio_pm_configure(value, TOTAL_GPIO_COMM);
-}
-
void soc_init_pre_device(void *chip_info)
{
/* Perform silicon specific init. */
@@ -193,7 +178,7 @@ void soc_init_pre_device(void *chip_info)
/* TODO(furquan): Get rid of this workaround once FSP is fixed. */
cnl_configure_pads(NULL, 0);
- soc_fill_gpio_pm_configuration();
+ soc_gpio_pm_configuration();
}
static void pci_domain_set_resources(struct device *dev)