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-rw-r--r--src/soc/intel/cannonlake/include/soc/iomap.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h
index 9cfb59e7d0..c66cde49a8 100644
--- a/src/soc/intel/cannonlake/include/soc/iomap.h
+++ b/src/soc/intel/cannonlake/include/soc/iomap.h
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
- * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2017-2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -68,6 +68,9 @@
#define HECI1_BASE_ADDRESS 0xfeda2000
+#define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB)
+#define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB)
+
/* PTT registers */
#define PTT_TXT_BASE_ADDRESS 0xfed30800
#define PTT_PRESENT 0x00070000