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-rw-r--r--src/soc/intel/cannonlake/chip.h13
-rw-r--r--src/soc/intel/cannonlake/romstage/fsp_params.c12
2 files changed, 21 insertions, 4 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 17afdd10da..507290f504 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -424,6 +424,19 @@ struct soc_intel_cannonlake_config {
* Bit 0: MISCCFG_GPDLCGEN
*/
uint8_t gpio_pm[TOTAL_GPIO_COMM];
+
+ /*
+ * Override CPU flex ratio value:
+ * CPU ratio value controls the maximum processor non-turbo ratio.
+ * Valid Range 0 to 63.
+ *
+ * In general descriptor provides option to set default cpu flex ratio.
+ * Default cpu flex ratio is 0 ensures booting with non-turbo max frequency.
+ * Thats the reason FSP skips cpu_ratio override if cpu_ratio is 0.
+ *
+ * Only override CPU flex ratio if don't want to boot with non-turbo max.
+ */
+ uint8_t cpu_ratio_override;
};
typedef struct soc_intel_cannonlake_config config_t;
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 996c13577e..5c74d4a1e0 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -74,10 +74,14 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
#endif
- /* Set CpuRatio to match existing MSR value */
- msr_t flex_ratio;
- flex_ratio = rdmsr(MSR_FLEX_RATIO);
- m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
+ if (config->cpu_ratio_override) {
+ m_cfg->CpuRatio = config->cpu_ratio_override;
+ } else {
+ /* Set CpuRatio to match existing MSR value */
+ msr_t flex_ratio;
+ flex_ratio = rdmsr(MSR_FLEX_RATIO);
+ m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
+ }
/* If ISH is enabled, enable ISH elements */
if (!dev)